• Guideline for Reproducible SiC MOSFET Thermal Characterization Based on Source-Drain Voltage

    Guideline for Reproducible SiC MOSFET Thermal Characterization Based on Source-Drain Voltage

    18 Min Read

    Abstract

    This paper aims to provide a guideline with respect to a reproducible thermal transient measurement for SiC MOSFETs. Although the thermal transient measurement based on sourcedrain voltage is a widely applied method for characterizing the thermal properties of MOSFETs, the approach developed for silicon-based devices may not be directly applicable to SiC devices. Therefore, this paper investigates the thermal transient measurement method for SiC MOSFETs using the source-drain voltage as the temperature-sensitive electrical parameter.

    A comprehensive investigation of its linearity, sensitivity, and stability toward yielding the thermal structure-property of the device has been carried out. The investigation includes two primary characterization procedures: temperature calibration and cooling curve measurement. The associated key testing conditions, such as gate voltages, sensing and heating currents, etc., are covered. The study examines the impact of these conditions on both static and dynamic performance to provide a better understanding of the reproducible thermal transient measurement for SiC MOSFETs.

    I. Introduction

    Silicon carbide (SiC) MOSFETs are becoming increasingly popular in a wide range of applications, such as electric vehicles, industrial drives, and high-voltage transmissions. SiC offers several advantages over silicon, including lower power losses at higher switching frequencies, higher operating temperatures, and withstanding higher voltages. However, to ensure safe operation and maximize the device’s lifetime, all these superior performances must be achieved within the maximum junction temperature limit. Therefore, thermal characterization of SiC MOSFETs is essential to define the boundaries.

    Thermal transient measurement is a widely accepted method to characterize the thermal properties of silicon (Si) power semiconductor devices. It has been recognized in several standards, such as JEDEC JESD 51-1 and JEDEC 51-14 and successfully applied to different applications over the past two decades, such as generating RC thermal models for electro-thermal simulation, packaging defect inspection, and junction-to-case thermal resistance measurement.

    However, directly applying this approach to SiC MOSFETs is still doubtful to some extent. For instance, SiC MOSFETs do not have a pn junction in the forward direction and have low on-state resistance, which imposes challenges to measure transient thermal response by the channel voltage. Meanwhile, trapped charge carriers in the gate region may cause second-level electrical disturbances and inevitably affect the extraction of thermal transient from the coupled electrical disturbance. In the state-of-the-art, the source-drain voltage is one of the most used temperature sensitivity electrical parameters (TSEP) for SiC MOSFETs.

    As shown in Fig. 1, the characterization consists of two major procedures, namely temperature calibration and cooling curve measurement. Improper selection of test conditions may result in misleading results. First, calibrating SiC MOSFETs for thermal transient measurement involves selecting the appropriate sensing current and gate voltage as step 1 shown in Fig. 1. While a sensing current of 1/1000 of the nominal current is commonly used for Si devices, it is however still under debate for SiC MOSFETs. Some studies use a small current below 1/1000 of the nominal current, while others suggest a much higher sensing current.

    Fig. 1. Circuit diagram of the thermal transient measurement for SiC MOSFETs

    Additionally, selecting the appropriate negative gate voltage is critical for fully turning off the MOSFET channel and allowing all injected sensing current to flow through the body diode. However, the methodology for selecting the optimal gate voltage value and its impact on the transient thermal impedance remains unclear. It is worth noting that previous studies have mainly focused on steady-state calibration results, but transient temperature measurement requires consideration of transient behaviors, which has not been fully addressed in the literature. In addition to the calibration procedure, the cooling curve measurement of SiC MOSFETs involves other parameters such as heating currents and the switching transient of the gate state.

    Previous studies have mainly focused on power cycling, where only the maximum and minimum temperature points are required. However, the investigation of thermal transient measurement with respect to the temperature dynamics across multiple time scales is limited. Electrical disturbances that occur at any point in time may lead to inaccurate thermal structure properties. Therefore, further investigation of the cooling curve measurement is also crucial. This paper comprehensively investigates the thermal transient measurement approach of SiC MOSFETs using Vsd as the TSEP and focuses on how to obtain more reproducible thermal structural information. Comparing to a preliminary conference version, the contributions of this article are three folds:

    • Evaluated the impact of key testing conditions, including the gate turn-off voltage and sensing current, on the calibration based on static and dynamic tests. Three criteria are proposed to quantify the sensing current and two methods are proposed to justify the gate voltage.
    • Investigated how various parameters affect cooling curve measurement in terms of static and dynamic responses.
    • Derived a guideline of how to perform a reproducible thermal transient measurement of SiC MOSFETs with a proper selection of testing conditions and parameters.

    II. Thermal Transient Measurement

    Fig.1 illustrates the two major steps to perform the thermal transient measurement for a SiC MOSFET, namely, the temperature calibration and cooling curve measurement. The calibration is to obtain the relationship between the TSEP and the device temperature, which is controlled by an external system (e.g., an oven, a dielectric bath, or a temperature-controlled cooling plate). The MOSFET body diode pn junction voltage Vsd shows a linear temperature dependence given a small sensing current going through the device. By measuring Vsd under various temperatures, the relation of Vsd = f(T) can be calibrated.

    Note that a low enough negative gate voltage has to be applied to completely shut the MOSFET channel off during this process (see Fig.2). In the second step, cooling curve measurement is carried out based on two current levels: one is the heating current (Iheat) to heat the device up, and the other is the sensing current for temperature monitoring with a negligible self-heating impact, as shown in Fig. 1 (Step 2).

    Fig. 2. Structure of a SiC MOSFET

    Once Vsd is measured, the inversely calibrated T = f−1 (Vsd) in step 1 converts the measured voltage into the temperature. However, the temperature calibration is developed based on static conditions but the cooling curve is derived from dynamic voltage responses. The compatibility of the two steps has a prerequisite that the electrical disturbance is short and negligible. However, reference pointed out that SiC MOSFETs have much longer electrical disturbance compared to Si devices. Its impacts on thermal transient measurement are not fully understood and will be investigated in the following two sections.

    III. Calibration: Impact of Sensing Current

    To obtain reliable thermal transient measurement for SiC MOSFETs, the sensing current needs to be carefully selected to achieve good linearity, sensitivity, and low power dissipation. Additionally, to minimize unwanted electrical disturbances, a short sensing current pulse is preferable. In this section, three criteria are proposed to quantify the impacts of sensing current.

    A. Impact of Sensing Current Density on Static Performance

    1) Linearity: pn-junction voltage Vpn is used as TSEP due to its linear temperature dependence, which is given by

    E 1

    where Eg is band gap, q is the elementary charge, kb is Boltzmann constant, and A is a device-specific factor. These parameters are either independent of or have weak dependence on temperature. When a constant sensing current density jsense is applied, Vpn varies linearly with temperature T. However, for SiC MOSFETs, the voltage drops across the drift region, contact, and metallization can contribute significantly to Vsd when a high sensing current is used.

    Fig. 3. Calibration curves for multiple sensing currents

    Moreover, at high temperatures and low current densities, the negative temperature coefficient of body diode results in a smaller Vpn. All above phenomenon can jeopardize the linear temperature dependence of Vsd and needs to be properly dealt. Fig. 3(a) shows the calibration results for different sensing currents ranging from 5 mA to 1000 mA. The proper selection of sensing current can be justified by the linearity between Vsd and temperature, which is further assessed by Pearson correlation coefficient ρlinear with 1 indicating perfect linearity

    E 2

    where cov denotes the covariance, and σ is the standard deviation. The left part of Table I lists that a sensing current of Isense = 100 mA gives the best linearity, whereas smaller and larger sensing currents result in a slightly worse performance.


    2) Sensitivity: A viable TSEP sampling hardware requires a sensitivity SVT above 1 mV/K, which is defined as

    E 3

    Given a constant sensing current density, the temperature derivative of (1) yields

    E 4

    It indicates that when Vpn dominates the device’s voltage drop, the sensitivity decreases with the sensing current due to its negative logarithmic dependency in (4) and is also validated in the left part of Table I. All scenarios listed in the table meet the 1 mV/K requirement. Note that a higher or a lower SVT can also be selected according to the specific acquisition system.

    TABLE I--CALIBRATION RESULTS UNDER DIFFERENT SENSING CURRENTS AND GATE TURN-OFF VOLTAGES.-

    3) Self Dissipation: To ensure accurate junction temperature measurement in the cooling phase, the self heating effect of the sensing current shall be negligible. A self-dissipation ratio is defined as

    E 5

    where Psense is the power dissipated by the sensing current which is generated by the measured TSEP voltage Vsd@Isense under Isense. Prate is the rated power dissipation of the tested device provided in datasheet. Generally, Prate can cause more than 100 C junction temperature increase. ηsd ≤ 1% implies that the temperature increase by the sensing current is less than 1 C (regarded as negligible here). Table I shows, except the cases of 500 mA and 1000 mA, all other scenarios meet the requirement of ηsd ≤ 1%.

    B. Impact of Sensing Current Density on Dynamic Performance

    During the period from 1 to 2 in Fig. 1, electrical and thermal transients occur simultaneously. This coupling poses challenge to extract the correct cooling curve of power devices. To address this issue, the standard JESD 51-1 introduces a delay time (tMD) to remove unwanted electrical transients plus a linear extrapolation to estimate the temperature at t = 0 s.

    However, SiC MOSFETs are likely to suffer from long tMD, e.g., more than 600 µs under Isense = 5 mA in Fig. 3(b). It is much longer than the time scale of the chip’s thermal transient and hinders getting an accurate thermal structure property. However, by increasing Isense to 100 mA, tMD reduces to an acceptable 42 µs. Further increasing the sensing current has a limited effect on reducing tMD but rapidly increases the self-dissipation ratio.

    Taking both static and dynamic performances into account, a sensing current of 100 mA achieves better overall performance for this study case.

    IV. Calibration: Impact of Gate Voltage

    A. Gate Turn-Off Voltage Selection

    TCAD simulation in Fig. 4 shows that the electronic density changes dramatically in the channel region when the gate voltage varies from 0 V to -4 V but remains steady for a gate voltage less than -6 V to fully turn the channel off. This behavior is fundamentally different from Si devices, where a gate voltage of 0 V is sufficient as shown in Fig. 5(a).

    Fig.-4.-The-electronic-density-distribution-of-the-SiC-MOSFET-under-different-Vgsoff-in-TCAD-simulation
    Fig. 5. Static and dynamic impacts of the gate voltages on SiC MOSFET

    Although existing studies have experimentally shown that Vgsoff = −6 V is enough to turn off the channel of SiC MOSFETs, it may not be applicable to all SiC MOSFETs due to different die designs and manufacturing processes. Different devices will be discussed in Section VI-C and the following part will focus on two methods for gate turn-off voltage selection.

    1) Method 1 – Output Characteristic under Sensing Current: Output characteristic curves of body diode under the sensing current range can shift significantly from each other in case of insufficient gate voltages, such as Vgs = −3 V in Fig. 5(b) but start to overlap as the gate voltage approaches -6 V. To quantify this effects, an electrical conductance gdiode at the sensing current is defined as

    E 6-7

    When the entire current flows through the internal body diode, the conductance is independent of gate voltage and becomes a constant. The minimum Vgs ensuring a completely-off channel can then be identified by (7), for example, Vgs = −4.5 V for this case study as shown in Fig. 5(c).

    2) Method 2 – Calibration Curves with Varied Gate Voltages: The calibration curves show the relationship between the sensing current and TSEP, and shall overlap with each other under various gate voltage provided a fully turned-off MOSFET channel. At the meantime, TSEP is linearly dependent on temperature. Therefore, similar to method 1, the criteria defined in (8) can be introduced to identify the minimum reasonable gate tun off voltage, which is a slightly different Vgs < −5 V than Vgs < −4.5 V as shown in Fig. 5(d).

    E 8
    B. Static and Dynamic Impacts of Gate Voltages

    The calibration results under various gate voltage are also evaluated with respect to the linearity, sensitivity, and self-dissipation ratio. The measured results and its analytical summary are show in Fig. 5(d) and the right-hand side of Table I. When the gate voltage changes from 0 V to -3 V, the linearity deteriorates significantly compared to the other gate voltages. This poor linearity indicates that the measured Vsd is not primarily determined by the pn junction.

    Moreover, by adjusting the gate turn-off voltage from 0 V to -8 V, the sensitivity and the self-dissipation ratio changes minorly. Regarding the dynamic behavior, the time delays under varied turn-on and turn-off gate voltages are investigated in Figs. 5(f) and (g), respectively. The effect of the gate voltage on the measurement delay time is almost negligible. Within the device’s maximum allowable gate voltage range, a lower gate turn-off voltage can improve the static behavior without significantly affecting the dynamic performance of the thermal transient measurement.

    V. Cooling Curve Measurement

    Once the calibration is completed, the established relationship between Vsd and temperature can be utilized for cooling curve measurements, where the selection and impacts of heating current, gate turn-on voltage etc. will be evaluated.

    A. Impact of Sensing Current

    Fig. 6(a) shows the cooling curves of a SiC MOSFET under same test conditions except the sensing current. Ideally, the two measurements shall overlap completely. However, the case with Isense = 5 mA takes 663 µs to reach the state 2 , comparing to only 42 µs under Isense = 100 mA. This is due to the fact that the body diode requires sufficient minority carrier charge accumulation to turn on, and it takes longer for a smaller sensing current.

    Fig. 6. Cooling curve measurement under varied conditions

    The above measurements validate the dynamic study in Section III-B. Furthermore, the frequency analysis in Fig. 6(b) shows measurements with Isense = 5 mA exhibit large high-frequency noises, while it decays rapidly when Isense = 100 mA. At a certain bandwidth ∆f of the measurement, the noise can be modeled as a Johnson-Nyquist form, that is,

    E 9

    where Rpn is the resistance of the body diode at Isense, i.e., Rpn ≈ kbT /qIsense. It indicates that the noise in the measured voltage diminishes with the square root of the sensing current. Thus, a higher sensing current is advantageous for both shorter electric transients and lower noise.

    B. Impact of Gate Turn-Off Voltage

    Fig. 6 c) illustrates a series of cooling curves measured under various gate voltages. (Note that each cooling measurement shares the same gate voltage with its used calibration curve, which can be found in Table I). Abnormal temperature rises at approximately 2×10−4 s can be observed with severely insufficient gate voltages (e.g., 0 V and -1 V) but disappears with gate voltages less than -3 V.

    This phenomenon is inconsistent with physical principles as the cooling stage does not involve any heat injection and therefore junction temperature rise shall not appear. Similar behavior is also observed with a conclusion of imperfect SiC MOSFET structure. Another reason for this inconsistency can be the insufficient gate turn-off voltage based on above findings. Moreover, temperature measurements go below the ambient temperature of 25 C for voltages less than -3 V but turn normal by further lowering voltage to -6 V and beyond.

    Similar effects can be observed in Fig. 6(d) where the thermal impedance curves, reflecting the thermal structure of a semiconductor package, remains unchanged until the sufficient enough gate voltage is applied. These inconsistencies underscore the significance of the gate turn-off voltage.

    C. Impact of Gate Turn-On Voltage and Heating Current

    Gate turn-on voltage decides the channel voltage drop in the heating stage. Together with the heating current, a higher power dissipation results in a higher junction temperature. A maximum temperature difference of up to 20 C and 80 C are observed in Fig. 6(e) and (g) for different Vgson and Iheat. The derived thermal impedance curves, however, barely change as shown in Fig. 6(f) and (h). Additionally, the measurement delay time remains unchanged. Thus, conclusion can be made that Vgson and Iheat have negligible affect on the thermal characterization given a sufficient gate turn-off voltage and sensing current.


    VI. A Guideline for Reproducible Transient Thermal Measurements of SiC MOSFETs


    A. Junction-to-Case Thermal Impedance Measurement

    Cooling curve measurement evaluates the thermal impedance from the device junction temperature to the ambient. More importantly, it can be used to identify the junction-to-case thermal impedance, which attracts more industrial interest. The JESD 51-14 standard clearly states the procedure by using transient dual interface approach. The overall principle is to conduct two transient thermal measurements of the identical device but with and without thermal interface material (denoted as tim and dry, respectively).

    The two derived thermal curves start to separate as soon as the heat flow enters the TIM layer due to the surface roughness between package and cold-plate. Same procedure is followed in this paper based on the testing platform in Fig. 7(a) and previously identified test conditions of Vgs_off = -6 V and Isense = 100 mA. Subsequently, the cooling curves and thermal impedance curves are obtained as shown in Fig. 7(b) and (c). A clear separation point, or namely junction-to-case thermal impedance, can be observed at 0.8 K/W in Fig. 7(c) and in the thermal structure function curve in Fig. 7(d).

    Fig. 7. Experimental measurement of junction-to-case thermal impedance of the SiC MOSFET
    B. Transient Thermal Measurement Guideline

    Based on the analysis and results discussed earlier, a flowchart to achieve a reproducible transient thermal measurement is provided in Fig. 8. It is evident that the gate turn-off voltage (Vgsoff) is a critical parameter that needs to be determined initially. Method 1 or 2 from Section IV-A can be applied. Certain margin can be added within the maximum gate voltage too as it benefits both static and dynamic states.

    Subsequently, the sensing current (Isense) should be carefully selected. Too large or small sensing currents may not be conducive to accurate transient thermal measurements. It is important to ensure that the pn-junction dominates the measured drain-source voltage (Vsd) in terms of linearity, sensitivity, self-dissipation ratio, and measurement delay. Both the static and dynamic states should be evaluated comprehensively.

    Fig. 8. A flowchart for reproducible transient thermal measurement.

    Once Vgsoff and Isense have been determined, the cooling curve measurement can be conducted accordingly. A final validation process can be added by varying the heating current (Iheat) or gate turn-on voltage (Vgsoff) to further validate the accuracy and reproducibility of the measurements.

    C. Viability Validation

    To validate the viability of the proposed flow, three additional devices from different vendors are tested with key information listed in Table II. Device 1 has been investigated in Section IV-V in detail. Fig. 9 shows the results of determining Vgsoff based on method 2. It is apparent that Vgsoff = −6 V, employed by multiple existing studies, is not sufficient enough for device 3 and 4 that require -10 V and -13 V to turn their channel off completely.

    Fig. 9. Selection of Vgsoff and Isense for additional three different devices listed in Table II

    But it should be noted that these two values exceed the maximum allowable gate voltages according to devices data sheet. It implies that the current thermal transient measurement method based on Vsd may not be applicable to device 3 and 4 without exceeding the maximum gate turn-off voltage. Moreover, the selection of Isense with respect to the dynamic performance can be found in Fig. 9 together with the corresponding static performances listed in Table II. 100 mA is a proper sensing current for all 4 devices due to the short tMD and negligible self dissipation. It should be noted that the sensing current is around 5.26 ‰ of the rated current of the SiC MOSFET, which is different from Si devices.

    TABLE II--COMPARISON OF DIFFERENT DEVICES

    VII. Conclusion

    This paper investigates the thermal characterization of SiC MOSFET based on the body diode source-drain voltage. Two key steps, namely the calibration and cooling curve measurement, are evaluated comprehensively. The selection of key testing conditions, i.e., sensing/heating currents, gate turn-off/turn-on voltages, are thoroughly assessed based on their impacts on the thermal characterization and the following conclusions are achieved:

    1. Low enough gate turn-off voltage shall be used in both calibration and cooling curve measurement to ensure a completely shut channel and correct thermal impedance measurement. However, the required negative gate voltage may exceed the maximum allowable range, which causes the current thermal transient measurement method based on Vsd being not available for these devices within the maximum allowable gate voltage.
    2. Insufficient sensing current deteriorates the dynamics in terms of longer electrical disturbance and more noises, while too large sensing current sacrifices the steady-state performance in particular of a large self dissipation ratio.
    3. Gate turn-on voltage and heating current have negligible impacts on the measured thermal impedance. The consistency of the thermal impedance under varied gate turn-on voltage or heating current can be used as a validation.

    Besides, a guide flowchart to perform reproducible transient thermal measurement for SiC MOSFETs is provided in this paper, which includes the selection of the electrical parameters and a validation process.

    Authors

    Yi Zhang, Yichi Zhang, Zhiliang Xu, Zhongxu Wang, Voon Hon Wong, Zhebie Lu, Antonio Caruso

    Original – Research Gate

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  • SiC Trench MOSFET with Depletion-Mode pMOS for Enhanced Short-Circuit Capability and Switching Performance

    SiC Trench MOSFET with Depletion-Mode pMOS for Enhanced Short-Circuit Capability and Switching Performance

    14 Min Read

    Abstract

    A novel 4H-SiC trench metal-oxide-semiconductor field-effect transistor (TMOS) with depletion-mode pMOS (D-pMOS) is proposed and investigated via TCAD simulation. It has an auxiliary gate electrode that controls the electrical connections of P-shield layers under the trench bottom through the D-pMOS. In linear operation, the D-pMOS is turned off and then the potential of the P-shield layers is raised with the auxiliary gate, which shrinks the width of the depletion region of the P-shield/N-drift junction to reduce the resistance of the JFET region. In the saturation operation, the saturation current density of the proposed TMOS is reduced, benefiting from its relatively large cell pitch.

    The design concept eases the tension between specific on-resistance and short circuit capabilities. Numerical simulation results show that the proposed TMOS exhibits a short circuit withstand time that is 1.92 times longer than that of the conventional TMOS. In addition, a drive tactic is introduced and optimized for the proposed TMOS, which requires only one set of gate drivers. Compared with the conventional TMOS, the switching performance is improved and the switching loss is reduced by 40%.

    1. Introduction

    Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with higher critical breakdown fields, lower switching loss, and better thermal conductivity are of interest to replace silicon-insulated gate bipolar transistors (Si IGBTs) in power electronic applications. This is particularly true for the electric vehicle (EV) industry today, where the range anxiety of driving an EV is the primary motivation for developing high-power-density and high-efficiency power systems. Starting with the milestone of the first SiC UMOSFET introduced by Cree Research, significant improvements in on-state resistance and power density have been achieved with the transition from the planar gate to trench gate.

    The fatal weakness of SiC trench-gate MOSFETs (TMOS) is a crowded electric field at the trench corner, which causes premature breakdown. The oxide electric field at the trench corner (ECorner) is recommended to be less than 4 MV/cm. To date, designs to suppress the ECorner have been extensively studied. In addition, some structures have been developed and commercialized, such as Rohm’s double-trench MOSFET and Infineon’s asymmetric-trench MOSFET. The introduction of the grounded P-shield regions under the trench bottom is an effective approach to suppress the electric field at the trench corners, but the specific on-resistance (RON, sp) is sacrificed due to the increase in the resistance of the junction field-effect transistor (RJFET).

    Y. Wang proposed an optimized UMOSFET with low RON, sp, by introducing an additional N-type layer under the grounded P-shield regions to attenuate RJFET. J. Wei proposed a novel MOSFET structure featuring both trench and planar channels, which increased the channel density and thus improved the trade-off relationship between RON, sp, and ECorner. M. Zhang proposed a new SiC trench MOSFET structure with self-biased p-shield, using an external self-biasing network, which reduces RJFET and keeps a low off-state oxide field. Based on that, Y. Xing introduced a depletion P-channel MOS (D-pMOS) to the conventional TMOS. The new structure adjusts the potential of the P-shield via the D-pMOS for low on-state resistance.

    Nevertheless, the saturation current density of TMOS also increases with increasing channel density and decreasing on-state resistance, which means that the short-circuit (SC) capability of TMOS is even weaker and the SC withstanding time (tSC) is shorter. T. Yang proposed an embedded JFET structure inside TMOS to reduce the peak SC current. W. Ni reported the optimization of the overlap region of the grounded P-shield layers to improve the trade-off relationship between RON, sp, and tSC. The major challenge, however, is to improve the trade-off relationship between RON, sp and SC capabilities in the development of SiC TMOS.

    In this article, a new design of 4H-SiC TMOS with depletion-mode pMOS (D-pMOS) is proposed and studied via Silvaco TCAD simulation. A D-pMOS is embedded into SiC MOSFET and an auxiliary gate electrode is introduced to control the electrical connections of P-shield layers under the trench bottom. The design concept significantly improves the trade-off relationship between RON, sp and SC capability. In addition, a drive method for the proposed TMOS is introduced to achieve lower switching loss.

    The subsequent sections of the paper are organized as follows. Section 2 introduces the device structure and design concept of the proposed TMOS. Section 3 presents the numerical simulation results and discussion, while Section 4 provides the conclusion.

    2. Device Structure and Design Concept

    Figure 1 shows the cross-sectional views of the conventional trench MOSFET with grounded P-shield layers (GP-TMOS) and the proposed TMOS with D-pMOS. The proposed TMOS is derived from the GP-TMOS, but it has two unique structural features.

    To create a depletion-mode pMOS, a lightly doped P-type layer is positioned between the P+ layer and the P-shield layer. In addition, the poly-Si gate is split into two parts, called the main gate (MG) and the auxiliary gate (AG). The MG controls the n-MOS, while the AG controls the D-pMOS. The two device structures share the device parameters as those listed in Table 1.

    Electronics 12 04764 g001a
    Electronics 12 04764 g001b

    Figure 1. Cross-sectional views of (a) the conventional GP-TMOS, and (b) the proposed TMOS.

    Table 1. Device parameters for TCAD simulations.

    Table 1. Device parameters for TCAD simulations

    The RJFET of the GP-TMOS consists of two parts, as shown in Figure 1a. RJFET1 is formed between the P-base and P-shield, and RJFET2 is formed between adjacent P-shield layers. They can be expressed as

    RJFET1 is formed between the P-base and P-shield, and RJFET2 is formed between adjacent P-shield layers

    Here, WGP is the horizontal distance of the P-shield layer beyond the gate trench. WD_P-shield is the depletion region width of the P-shield/N-drift junction. WD_P-base is the depletion region width of the P-base/N-drift junction. tB is the vertical distance between P-base and P-shield. TP-shield is the thickness of the P-shield layer. VD is the potential of the P-shield/N-drift junction. According to Equation (3), the P-shield layer potential VD determines the extent of the depletion region in the JFET region of TMOS.

    In the forward on-state, the P-shield layer of the proposed TMOS is disconnected from the source electrode by turning off the D-pMOS, and its potential is affected and increased by the voltage of the AG. Figure 2 shows the current density distributions for the GP-TMOS and the proposed TMOS at VMG = 18 V and VAG = 18 V. In the linear operation (Vds = 1 V), the depletion region width (WD) of the P-shield/N-drift junction for the proposed TMOS is smaller than that of the GP-TMOS, as illustrated in Figure 2a,b.

    The current path width of the proposed TMOS is widened to decrease RJFET. In the saturation operation (Vds = 800 V), WD for the proposed TMOS is the same as that of the GP-TMOS, as well as the current path width in a single-cell pitch, as shown in Figure 2c,d. This indicates that RJFET1 and RJFET2 of the proposed TMOS are equal to those of the GP-TMOS in a single-cell pitch. Due to a relatively large cell pitch, the saturation current (Jsat) of the proposed TMOS can be remarkably reduced for the same active area. Thus, the proposed TMOS achieves a superior tradeoff relationship between RON, sp and SC capability.

    Electronics 12 04764 g002

    Figure 2. Current density distributions of two devices. (a) GP-TMOS at Vds = 1 V; (b) the proposed TMOS at Vds = 1 V; (c) GP-TMOS at Vds = 800 V and (d) the proposed TMOS at Vds = 800 V.

    Figure 3a depicts the energy band diagram of the sandwiched P-type layers along the cutline A-A’ (shown in Figure 1b). When VAG = 0 V, the hole barrier between the P+ layer and the P-shield layer is small. The lightly doped P- layer can transport holes from the P-shield to P+, as shown in Figure 3b, indicating that the P-shield layer is grounded.

    When VAG = 18 V, the EV from the P-shield layer to the P- layer decreases, resulting in a hole barrier. This is because the lightly doped P-layer is completely depleted, preventing holes’ transportation from the P-shield layer to the P+ layer, as shown in Figure 3c. This means that the P-shield layer is disconnected from the source electrode and is floating.

    Electronics 12 04764 g003

    Figure 3. (a) Energy band diagram of the sandwiched P-type layers along the cutline A-A’, and operation mechanisms at (bVAG = 0 V and (cVAG =18 V.

    In the blocking voltage state, the P-shield layer of the proposed TMOS is connected to the source electrode by turning on the D-pMOS, similar to that of the GP-TMOS. The grounded P-shield layer protects the gate oxide from the high electric field, and then maintains a reliable blocking high voltage capability.

    During the switching transient, the P-shield layer of the proposed TMOS is also connected to the source electrode for safe operation. This is because the TMOS with floating P-shield layers has a notorious drawback, which is called dynamic on-resistance degradation. The proposed TMOS has an additional gate electrode, but only one set of gate drivers is required, as shown in Figure 4a.

    Using two gate drive resistances, RAG-g and RMG-g, nMOS and D-pMOS can operate asynchronously. Figure 4b shows the waveforms of the MG voltage and AG voltage. The D-pMOS is set to turn off after the nMOS has turned on, keeping the P-shield layer grounded during the switching transient for reliable dynamic operation.

    Electronics 12 04764 g004

    Figure 4. (a) Simplified diagram of the gate driver principle; (b) waveforms of two gate voltages.

    3. Simulation Results and Discussion

    The physical models include recombination models, incomplete ionization models, mobility models, bandgap narrowing models, and impact ionization models. It is noted that the Giga module is employed to capture self-heating effects and thermoelectric powers. The channel mobility of the TMOS is fixed to 50 cm2/V·s. In this comparison, the numerical simulation parameters are identical.

    Figure 5 shows the impact of the width, WP-, and the doping concentration of the lightly doped P- layer, NP-, on the RON, sp (VMG = 18 V, VAG = 18 V and Jds = 200 A/cm2) and Jsat (VMG = 18 V, VAG = 18 V and Vds = 800 V) values of the proposed TMOS. As WP- and NP- decrease, RON, sp decreases and then remains at a fixed value. This is because the electrical connection state of the P-shield layer changes from grounded to floating. A small WP- and a low NP- facilitate the depletion of the P- layer. In contrast, Jsat increases as WP- and NP- decrease. The maximum Jsat is still below 6.5 kV/cm2 due to the relatively large cell pitch for the proposed TMOS.

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    Figure 5. Impact of WP- and NP- on (aRON, sp and (bJsat for the proposed TMOS.

    Figure 6 shows the forward output characteristics for the proposed TMOS and the GP-TMOS. The WP- and NP- of the proposed TMOS are 1.0 μm and 4.0 × 1016 cm−3. The RON, sp of the proposed TMOS and the GP-TMOS is 2.95 mΩ·cm2 and 2.53 mΩ·cm2 with Vgs = 18 V and Jds = 200 A/cm2, respectively. The RON, sp of the proposed TMOS is approximately 10% higher than that of the GP-TMOS, whereas the Jsat of the proposed TMOS is substantially reduced from 10.22 kA/cm2 to 5.85 kA/cm2, a reduction of nearly 43%. 

    Figure 7 shows the blocking voltage characteristics. The P-shield layer of the proposed TMOS is grounded (VMG = 0 V and VAG = 0 V). The blocking behavior of the proposed TMOS is similar to that of the GP-TMOS. The maximum electric field of both is located at the P-shield/N-drift junction.

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    Figure 6. The output characteristics of the proposed TMOS and the GP-TMOS.

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    Figure 7. The blocking characteristics of the proposed TMOS and the GP-TMOS.

    Figure 8 displays the SC-simulated waveforms of the current density, Jds, and the temperature profile for both the proposed TMOS and the GP-TMOS with Vgs = 18 V and Vds = 800.0 V. The peak current density of the proposed TMOS is decreased by 30%. Therefore, the junction temperature of the proposed TMOS is also lower, which could postpone the triggering of thermal runaway. Compared to the GP-TMOS, the SC withstanding time (tSC) of the proposed TMOS increases from 5.2 μs to 10.0 μs, which is approximately 1.92 times longer. The new design concept significantly eases the tension between RON, sp and tSC.

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    Figure 8. Short-circuit waveforms of the proposed TMOS and the GP-TMOS.

    Figure 9 shows the schematic diagram of the dynamic switching simulation. The switching voltage and current are set to 800.0 V and 20.0 A, respectively. The stray inductance in the power loop is 5 nH. Figure 10 shows the influences of the AG resistance, RAG-g, and the doping concentration of the P-layer, NP-, on the power loss of the proposed TMOS. The power loss includes turn on loss and turn off loss. The RMG-g is set to 5, 10, and 20 Ω, and the dependence relationships are shown in Figure 10a–c. As NP- and RAG-g increase, the power loss decreases for various RMG-g.

    This is caused by the change in the P-shield layer’s connection state during the switching transient, from a floating state to a grounded state. The TMOS with floating P-shield layers has poor dynamic performance and exhibits relatively higher switching loss. As NP- increases, a relatively high AG voltage is required to fully deplete the P-layer, which affects the threshold voltage of the D-pMOS. On the other hand, increasing RAG-g delays the triggering of the D-pMOS’s turn off during the turn on stage of the proposed TMOS. Both of the above methods can achieve grounded P-shield layers during the switching on transient of the proposed TMOS. 

    Figure 11 shows the switching waveforms of the proposed TMOS under two conditions. Condition I is NP- = 1 × 1016 cm−3 and RAG-g = 1 Ω, while condition II is NP- = 4 × 1016 cm−3 and RAG-g = 20 Ω. Under condition I, the D-pMOS turns off before the nMOS turns on. The turn on behavior of the proposed TMOS is the same as that of the TMOS with floating P-shield layers, where the expanding depletion region of the P-shield/N-drift junction cannot shrink back immediately, resulting in a slower switching speed and dynamic RON degradation. Under condition II, the D-pMOS turns off after the nMOS turns on. The switching performance is obviously improved by grounding the P-shield.

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    Figure 9. The schematic diagram of the dynamic switching simulation.

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    Figure 10. Influences of RAG-g and NP- on the power loss, when (aRMG-g = 5 Ω, (bRMG-g = 10 Ω, and (cRMG-g = 20 Ω.

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    Figure 11. Switching waveforms of the proposed TMOS for condition I (NP- = 1 × 1016 cm−3RAG-g = 1 Ω) and condition II (NP- = 4 × 1016 cm−3RAG-g = 20 Ω).

    Figure 12 compares the switching waveforms for the proposed TMOS and the GP-TMOS. Both the gate resistance of the GP-TMOS and the MG resistance of the proposed TMOS are set to 10 Ω. The NP- and RAG-g of the proposed TMOS are 4.0 × 1016 cm−3 and 5 Ω, respectively. The optimized AG resistance ensures a reliable switching operation without dynamic RON degradation. Moreover, the switching speed of the proposed TMOS is improved, due to the split-gate structure.

    The proposed TMOS exhibits a shorter switching time as a result of its lower gate drain capacitance. The tON and tOFF of the SFP-SG-MOSFET are both smaller than those of the GP-TMOS and decrease by 48.7% and 74%, respectively. The switching power losses are calculated as shown in Figure 13. The turn on loss (EON) for the proposed TMOS is 1.05 mJ/cm2, which is reduced by about 35.5% compared to the GP-TMOS. The turn off loss (EOFF) for the proposed TMOS is 0.38 mJ/cm2, which is reduced by about 50% compared to that of the GP-TMOS.

    The total switching loss (ESW) for the proposed TMOS is as low as 1.43 mJ/cm2, showing a 40% reduction compared to that of the GP-TMOS. The performance comparison of the two devices is offered in Table 2.

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    Figure 12. Switching waveforms of the proposed TMOS and the GP-TMOS.

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    Figure 13. Switching losses of the proposed TMOS and the GP-TMOS.

    Table 2. Comparison of two structure device characteristics.

    Table 2. Comparison of two structure device characteristics.

    4. Conclusions

    A novel 4H-SiC-trench MOSFET with a depletion-mode pMOS (D-pMOS) is proposed and investigated numerically. Using the D-pMOS, the potential of the P-shield layer of the proposed TMOS can be controlled using an auxiliary gate. The width of the depletion region of the P-shield/N-drift junction is adaptively modulated in the linear and saturation operating regions.

    Consequently, the proposed TMOS acquires a superior RON, sptSC tradeoff, achieving a 92% longer short-circuit withstanding time than that of the GP-TMOS. Moreover, the proposed TMOS flexibly utilizes two different gate resistances, while using only one set of gate drivers, which suppresses the dynamic RON degradation and further reduces switching loss. It achieves a 40% lower switching loss than that of the GP-TMOS. The superior SC capability and lower switching dissipation of the proposed TMOS hold the promise of enhancing the efficiency and reliability of power electronic systems.

    Authors

    Hengyu Yu, Limeng Shi, Monikuntala Bhattacharya, Michael Jin, Jiashu Qian, Anant K. Agarwal

    Original – MDPI

    Comments Off on SiC Trench MOSFET with Depletion-Mode pMOS for Enhanced Short-Circuit Capability and Switching Performance
  • A Basic Design Tool for Grid-Connected AC–DC Converters Using Silcon Carbide MOSFETs

    A Basic Design Tool for Grid-Connected AC–DC Converters Using Silcon Carbide MOSFETs

    29 Min Read

    Abstract

    The design and optimization of power converters is a key factor in the growth and development of the power electronics field. However, the process of designing a power converter is not straightforward, and engineers often rely on experience and intuition, sometimes requiring time-consuming computer simulations. This paper presents a tool for the basic design of grid-connected AC–DC converters. The design tool takes specifications and operating conditions for two-level and three-level NPC converter topologies and derives a draft design.

    The tool calculates the input filter’s electrical parameters, the converter’s losses, the temperature rise of the power semiconductor devices, and the ripple current and voltage of the DC-link capacitor. In order to validate the proposed design tool, four AC–DC converters using SiC MOSFETs were designed. Based on the design results, simulation models and prototypes were fabricated to verify the performance and confirm that the proposed design tool can be used in the basic design process of converters.

    1. Introduction

    As the field of power electronics continues to evolve, the design and optimization of power converters is a key factor in the efficient conversion and utilization of energy. Power converters in various forms, such as AC–DC converters and DC–DC converters, play an important role in power management, motor control, and more in a variety of applications such as renewable energy systems, electric vehicles, industrial automation, and home appliances. The ability to design these power converters precisely and efficiently is crucial for meeting the energy efficiency, reliability, and sustainability requirements of the ever-evolving energy industry [1].

    However, the process of designing a power converter is far from simple. There are complex tradeoffs between design features such as the power circuit structure, control scheme, and switching frequency and performance metrics such as efficiency, voltage ripple, and current ripple. Engineers designing power converters often rely on experience and intuition, and in some cases, complex computer simulations, to achieve optimal results. Even experienced professionals can find it difficult to design with new converter topologies, control schemes, etc., and it can take a lot of trial and error to learn how to do it, especially for newcomers to the field [2,3].

    To solve this problem, studies have been conducted on procedures and methods for designing various types of power converters. References [4,5,6] present step-by-step procedures for designing power converters with specific converter topologies or introduce tools that can assist in the design. These works are mainly aimed at finding the optimal design point to achieve the targeted performance metrics when the basic design of the power converter is already completed. However, this approach can be difficult for someone not already familiar with the design of this type of converter.

    Recently, methods using artificial intelligence (AI) have been studied to automate and reduce the reliance on experts in the converter and controller design phase [7,8,9,10]. These methods are well suited for use in the optimization design phase for specific target systems. However, AI-based design methods have the disadvantage of requiring simulations under various specifications and operating conditions to collect data, and the selection of appropriate training methods and the training process may require a considerable amount of resources.

    Alternatively, basic power converter design tools are available, often provided by power semiconductor manufacturers [11,12]. However, the applicable converter topologies are limited, and device selection is also limited by the only components manufactured by the design tool vendor.

    To address these issues, this paper introduces a general converter design tool for power converter design. The research project “Development of High Efficiency Power Converter based on Multidisciplinary Design and Optimization Platform”, funded by the Korea Institute of Energy Technology and Planning (KETEP), aims to build and operate an open web-based design tool for various power conversion systems based on wide-band-gap (WBG) semiconductors [13].

    The design tool proposed in this paper is intended to be used in the basic design phase and is intended to quickly check feasibility or to quickly see how a particular performance varies as a function of parameter variation. The intention is to save the user of the design tool the effort of calculating formulas or building simulation models by hand. The tool is a synthesis of state-of-the-art research and practical engineering expertise and aims to simplify and popularize the process of power converter design and optimization. It provides engineers and researchers with an intuitive and user-friendly interface, allowing them to efficiently explore different design outcomes with a large number of degrees of freedom. It enables them to optimize the design parameters and ultimately deliver a high-performance solution for their specific needs.

    These design tools can help accelerate the development of power conversion systems, foster innovation, and enable the rapid adoption of new technologies. Furthermore, they have the potential to popularize power conversion design knowledge. The popularization of this knowledge can play an important role in the development of new technologies and paving the way for a more sustainable and efficient future in power electronics.

    This paper introduces a general power conversion design tool for grid-connected AC–DC converters as part of the general converter design tool. The design tool developed requires the ability to allow the user to select different types of components available on the market during the design process. For this purpose, it is difficult to use data that must be obtained through complex experiments, and it is possible to use only the level of information disclosed in the datasheets provided by the manufacturers of the devices. The proposed design tool also aims to have simple formulas and design procedures so that they can be used in a lightweight web-based design tool.

    The proposed design tool primarily tackles the complexity inherent in power converter design. While traditional design methods heavily rely on complex computer simulations, the proposed tool simplifies this aspect, allowing for faster, more rapid, and more accessible design iterations. By making the design process more accessible and less dependent on deep expertise, the proposed tool helps to popularize power converter design knowledge, which is crucial for promoting innovation in the field.

    In the next section, the procedure for the basic system design of an AC–DC converter is presented, and the formulas used in each design step are derived. Based on the proposed design procedure, the design of converters of various specifications was carried out, and simulation models and prototypes were produced based on the designed parameters to verify the results of the design tool.

    2. Design Procedures

    This paper presents a design tool for grid-connected three-phase AC–DC converters using SiC MOSFETs among various types of power conversion devices. The design tool aims to facilitate the drafting of designs by engineers with little experience in converter design. Figure 1 shows the design procedure. Viewing the converter as an electrical circuit composed of lumped elements, the basic specifications, such as the input and output voltages, capacity, and converter topology, are first selected. Limits are set on the efficiency, voltage and current ripple, and temperature rise of the semiconductors, and the switching devices are selected.

    The input parameters include operating conditions such as the switching frequency and power factor, along with the previously selected items. Based on the input parameters, the tool calculates the ripple of the input current, the voltage and current ripple of the DC-link, derives the electrical parameters of the input filter and the DC-link capacitor, and calculates the converter loss and temperature rise to check whether the limit conditions are met.

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    Figure 1. Grid-connected AC–DC converter design procedure.

    However, this tool is intended for use in the basic design phase of a converter. In order for the web-based design tool to display design results quickly, the design procedure is based on simple formulas, and a certain amount of error is allowed. To develop a real product-level converter, more detailed design steps are required.

    The component-level design of passive devices, such as inductors used in converters, component placement and mechanical structure design for power density optimization, and the electromagnetic field analysis and heat distribution analysis, which require finite element analysis, are not covered in this paper. The process and formulas used in the design tool are as follows.

    2.1. Input Filter Design Procedure

    In a grid-connected AC–DC converter, the purpose of the input filter is to reduce current harmonics at the input side caused by voltage harmonics generated by PWM switching. As an input filter circuit, a simple inductor or an LCL filter consisting of two inductors and one capacitor is commonly used. The design tool in this paper exploits an LCL filter that has high harmonic rejection performance per unit inductance. 

    Figure 2 shows the structure of the AC–DC converter and the LCL filter discussed in this paper. Lc and Lg represent the converter-side and grid-side inductors, respectively, and the filter capacitor, Cf, is connected in series with the damping resistor, Rd. The power stack is represented by a three-phase, two-level (2L) voltage-type inverter structure, which assumes the use of a three-phase, two-level or three-level (3L)-NPC converter in this paper.

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    Figure 2. Grid-connected AC–DC converter structure with LCL filter.

    Ignoring the effect of damping resistors in the converter structure of Figure 2, the relationship between voltage harmonics and current harmonics can be expressed as follows.

    where ig is the grid-side current and vc is the output voltage at the converter side. The order-specific harmonics of the output voltage due to the switching of the converter can be calculated analytically [14]. With the limits of the target harmonic currents for each order, the input filter can be designed using the relationship in (1).

    Table 1, Table 2 and Table 3 show the current harmonic limits by order of the current harmonic regulations IEEE-519 [15] and IEEE-1547 [16], which are widely used in designing grid-connected AC–DC converters. Studies on designing input filters have used the relationship in (1) to select input filter parameters that ensure that the voltage harmonics caused by the PWM of the converter do not exceed the current harmonic limits of each regulation [17,18].

    Table 1. Current harmonic limits according to the IEEE 519 standard [15].

    Table 2. Odd harmonic current distortion limit in percent of rated current (Irateda according to IEEE 1547 [16].

    Table 3. Even harmonic current distortion limit in percent of rated current (Irateda according to IEEE 1547 [16].

    However, this approach may not be appropriate for converters using SiC MOSFETs. As shown by the relationship in (1), harmonics in the grid current are caused by harmonics in the output voltage due to the PWM operation of the converter. The output voltage harmonics can be roughly divided into two classes according to their order: higher-order harmonics around multiples of the PWM switching frequency and lower-order harmonics corresponding to multiples of the fundamental wave, such as the 5th, 7th, 11th, etc.

    The higher-order voltage harmonics can be calculated analytically according to the PWM method by obtaining the magnitude of the harmonic voltage of each order, and filter parameters can be designed accordingly to limit the harmonic current of that order to a target value or less.

    However, higher-order harmonics often account for a smaller proportion of the total current harmonic component generated by a grid-tied converter than lower-order harmonics. This is because higher-order harmonics have higher frequencies and are more easily attenuated by the input filters.

    This is especially true for converters using SiC MOSFETs, which often have switching frequencies of tens of kHz or more. Furthermore, popular grid input current harmonic regulations, IEEE 519 [15] and IEEE 1547 [16], limit the harmonic frequency to no more than the 50th order of the fundamental wave. For converters using SiC MOSFETs, most have switching frequencies above 20 kHz, so the higher-order harmonics associated with the switching frequency are well beyond the 50th order when referenced to the typical grid frequency of 60 Hz, which is outside the harmonic regulation criteria.

    When using input filters to satisfy grid current harmonics regulations, it is then necessary to design them with low-order current harmonics in mind, but it is difficult to accurately calculate the magnitude of the voltage harmonics that cause low-order current harmonics.

    Low-order output voltage harmonics are due to the non-ideal output characteristics of the converter, such as dead time and a voltage drop across switching elements, and are difficult to obtain analytically. In addition, for converters using SiC MOSFETs with fast switching frequencies, harmonic current controllers can be used to significantly suppress low-order harmonics [17]. In practice, harmonic current controllers are often used, which can lead to overly large filter designs if their effects are not considered. However, the harmonic control performance of the controller is also difficult to accurately estimate at the filter design stage.

    In this paper, an input filter design method based on limiting the maximum value of the ripple of the converter-side current below a certain value is used, rather than limiting the grid current harmonics below a certain value according to the regulations of [15,16], etc. The design procedure of the input filter is shown in Figure 3, and the detailed design process is as follows.

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    Figure 3. Inpul filter design procedure.

    • Select system specifications and operating conditions. Select the grid voltage, grid frequency, converter type (2L or 3L-NPC), switching frequency, DC-link voltage, and rated current.

    • Calculate ripple current and select converter side inductance. Set the converter-side ripple current limit. Select the limit value of the peak-to-peak amplitude of the current ripple relative to the rated current and calculate the converter-side inductor value that satisfies the ripple current according to the operating conditions. The peak-to-peak amplitude of the ripple current generated by the converter is determined by the operating conditions, and the instantaneous phase angle and can be expressed as (2) [18].

    where Vdc is the DC-link voltage, Ts is the switching period, and r(m,θ) is a function of the voltage modulation index (m) and the output voltage phase angle (θ). The magnitude of the instantaneous current ripple depends on the phase angle, but the proposed method calculates the magnitude of the current ripple based on the output voltage at a phase angle of 90°.

    In general, the power factor of a grid-connected converter is close to unity, so the output voltage and current are almost in-phase, and the magnitude of the current flowing in the converter is maximized around 90 degrees. Therefore, when considering the maximum current flowing through the converter due to current ripple, it is appropriate to base the design on the value when the phase angle is 90°. The converter-side inductance (Lc) value that satisfies the magnitude of the ripple current can be selected by using (2).

    • Select capacitance and grid-side inductance. The larger the capacitor of the LCL filter, the better it can absorb the converter’s ripple current and reduce the harmonics of the grid-side current. However, the capacitor in the input filter introduces reactive power at the grid side and changes the grid side power factor. Typically, the reactive power flowing into the capacitor is limited to 2–5% of the apparent power in the design of the input filter [19]. The proposed design tool takes the reactive power value of the capacitor as input and selects the capacitor divisor of the corresponding filter. The formula for selecting the capacitance value is shown in (3).

    where S is the apparent power of the converter, ω is the frequency of the grid, Vph is the phase voltage of the grid, and R is the ratio of the reactive power to the apparent power. In studies dealing with LCL filter design, the values of the grid-side inductance and the converter-side inductance are often chosen to be equal. This is because, when the resonant frequency of the LCL filter is first determined, equalizing the two inductance values results in the smallest magnitude of the total inductance [20], i.e., the harmonics of the grid current can be reduced the most with the same inductance value.

    However, in this paper, the filter is designed based on the ripple current on the converter side, not the current harmonics delivered to the grid. In the case of converters using SiC MOSFETs, the low-order harmonics that contribute most to the grid current harmonics can be significantly suppressed by current controllers, so the proposed method focuses more on the converter-side inductor in the total inductance used in the input filter. In this paper, the grid-side inductance is selected as one-third of the converter-side inductance.

    • Check the resonant frequency of the input filter. The resonant frequency (fres) of the input filter should be less than one-half of the sampling frequency (fs) according to the Nyquist sampling theory, and it should be higher than the bandwidth (fb) of the current controller to avoid affecting the current control behavior [21].

    Finally, check whether the parameters of the input filter selected satisfies (4), and if not, adjust the capacitance value so that the resonant frequency satisfy the limitation of (4).

    • Select damping resistor. The LCL filter theoretically has zero impedance at its resonant frequency. The damping resistor is used to provide impedance at this time to suppress the oscillation of the current at the resonant frequency. For this purpose, the value of the damping resistor is designed to be similar to the impedance of the capacitor connected in series at the resonant frequency [22], and in this paper, it is selected as one-third of the impedance of the capacitor at the resonant frequency.

    2.2. Calculating Losses and Temperature Rise

    The losses of the converter covered in this paper are composed of the losses of the power semiconductor and the losses of the input filter. The losses are calculated based on the given converter specifications and operating conditions, and the junction temperature is estimated using the thermal resistance information of the heat sink where the power semiconductor is installed.

    The losses of the power semiconductor can be divided into conduction losses and switching losses. The conduction losses of SiC MOSFETs and diodes are calculated using the RdsRd, and Vf0 information in the datasheet, as shown in (6) and (7), respectively, and the switching losses of SiC MOSFETs are calculated using the datasheet loss data, as expressed in (8).

    where Rds is the equivalent resistance when the SiC MOSFET is turned on and Rd and Vfo are the equivalent resistance and threshold voltage when the diode is turned on, respectively. Irms is the rms value of the current flowing in each power semiconductor device, fsw is the switching frequency, s(θ) is duration when the current is flowing in that semiconductor device, Iavg is the average current in the current flowing section, Vdc is the DC-link voltage, Vtest is the test voltage indicated in the switching loss data in the datasheet, and Eon/off is the loss function extracted from the on and off switching loss data in the datasheet. The gate resistance is inputted by the user and reflected in the determination of Rds and Eon/off.

    Equation (8) uses the average current in the conducting section to calculate the switching losses under the assumption that the current flowing in the device at the time of switching is proportional to the switching losses. In practice, the two are not exactly proportional. In general, for SiC MOSFETs, there is a slight exponential increase in switching losses as the current flowing through the device at the time of switching increases.

    As a result, the switching losses calculated from the average current tend to be smaller than the actual switching losses at higher load currents, leading to calculation errors. However, since the design tool presented in this paper is intended to be used in the basic design phase for feasibility checks, this level of error can be justified. Overcurrent and overvoltage due to parasitic components like stray inductance also affect the switching loss [23]. However, the parasitic component cannot be anticipated during the basic design phase, so it is not reflected.

    Figure 4 shows the leg structure of the two-level and three-level converters covered in this design tool, and the output voltage command and output current of the converter are shown in (9) and (10).

    where V and I represent the magnitude of the output voltage command and output current, respectively, ω is the frequency of the grid, and φ is the load angle. In order to calculate the loss of each power semiconductor device, the operating region can be divided into four according to sign of output voltage command and output current. 

    Figure 5 shows the four operating areas with the state of the output voltage command and current. Table 4 summarizes the current-carrying devices and devices where switching losses occur in each operating area for 2L and 3L-NPC converters. Using Figure 5 and Table 4, it is possible to calculate the rms value of the current flowing through each power semiconductor element, the average current in the section where the current flows, and substitute the values into (6)–(8) to calculate the loss for each element in each converter, as shown in Table 5 and Table 6.

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    Figure 4. Leg configuration of AC–DC converters.

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    Figure 5. Operating area classification.

    Table 4. Switch operation according to operating area.

    Table 5. Power semiconductor loss for 2L converter.

    Table 6. Power semiconductor loss for 3L-NPC converter.

    The calculated losses of the power semiconductor are used to calculate the junction temperature rise of the power semiconductor. Figure 6 shows the heat transfer circuit model used to calculate the temperature rise in this paper. The losses generated by the power semiconductor are denoted as Ploss, and the thermal resistance from the junction of the power semiconductor to the case, the thermal resistance from the case to the heat sink, and the thermal resistance from the heat sink to the atmosphere are denoted as Rth,jcRth,ch, and Rth,ha, respectively. TjunctionTcaseTheatsink, and Tamb represent the junction, case, heatsink, and ambient temperatures, respectively.

    The heat capacity of each part is not considered, but only steady-state losses and thermal resistance are considered to calculate the junction temperature. Rth,jc and Rth,ch use the datasheet values of the semiconductor device, and Rth,ha of the heat sink can be entered to be used to calculate the temperature rise, as shown in (11).

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    Figure 6. Heat transfer circuit.

    More precisely, thermal resistance could be expressed as a function of temperature [24]. However, as shown in [24], for accurate modeling, the parameters should be obtained through testing for each component used in the converter, which is difficult to achieve with a basic design tool for various different types of components. The thermal resistance in this paper uses nominal values from the datasheet.

    Most of the losses in the input filter come from the inductor. The loss of the inductor is determined by the design conditions, such as the core and winding used in the inductor, and the operating conditions, such as the magnitude and frequency of the voltage and current applied to the inductor. The conduction losses of an inductor are calculated using the resistance calculated from the cross-sectional area and length of the inductor windings, and the effective value of the current flowing in the inductor and the iron losses are calculated using the Steinmetz equation shown in (12) [25].

    The coefficients required for the Steinmetz equation were obtained from the core’s datasheet information and added together by calculating the losses at the fundamental and switching frequencies. The flux density (B) was calculated using the magnitude of the fundamental wave current and the maximum ripple current magnitude, calculated using (2).

    2.3. DC-Link Voltage, Current Ripple Calculations

    The design tool in this paper derives the minimum DC-link capacitance values required during the converter design process. With the given system specifications and operating conditions, the DC-link capacitor currents of the 2L and 3L-NPC converters (iC of the 2L converter and iC1/iC2 of the 3L-NPC converter in Figure 4) can be calculated analytically, as shown in (13) and (14), respectively [26,27]. Table 7 shows the detailed formulas for the parameters used in (14).

    Table 7. Expressions of A, B, C, and D in (14).

    Taking the limit value of the voltage ripple as the input, the minimum value of the DC-link capacitor that satisfies the limit value can be selected as follows [26].

    The tool selects the minimum value of the DC-link capacitor through equation (15) and derives the minimum value of the ripple current rating of the capacitor through (13) or (14).

    3. Design Examples

    Many cases of grid-connected AC–DC converters were designed using the converter design tool introduced in this paper. Table 8 shows the specifications and operating conditions of the design cases. All of them are 10 kVA-class grid-connected AC–DC converters and use 2L and 3L-NPC NPC converter topologies.

    The grid to which they are connected is assumed to be typical three-phase 380 V 60 Hz converters. The current ripple ratio indicates the magnitude of the ripple current relative to the rated current. Cases 1 and 2 and cases 3 and 4 have identical specifications except for the current ripple specification, resulting in designs with different input filters.

    Table 8. Specification and operating conditions for design cases.

    Table 9 shows the minimum values of the input filter and DC-link capacitance derived from the design tool. In (2), the current ripple magnitude of the 2L converter is generally larger compared to the 3L-NPC converter, resulting in a larger inductance despite the higher current ripple limit of the 2L converter.

    The minimum value of the DC-link capacitor resulting from the design is less than 10 μF, so in practice, the converter design should be based on selecting a capacitor that meets the current ripple rating. In such a design, the capacitance of the actual capacitor used is considerably larger than the minimum capacitance derived from the design tool, so that the voltage ripple caused by the current ripple is negligible.

    Table 9. Input filter design results.

    4. Simulation and Experimental Results

    Based on the results of the design tool introduced in this paper, simulation models and prototypes were produced and compared with the design values. For the four cases of circuits in Table 8 and Table 9, simulation models were created using PSIM (version 9.0), and prototypes were fabricated and compared with the experimental results. 

    Figure 7 is a photo of the experimental set of one of the fabricated prototypes. The current ripple of the fabricated converter was measured using an oscilloscope, and the efficiency was measured using a power meter. The temperature rise was measured by attaching an NTC to the heatsink where the power semiconductor was installed.

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    Figure 7. Experimental setup with prototype converter.

    Figure 8 shows the waveforms of the fabricated simulation and the prototype. They represent the input line voltage, converter current, and grid current, respectively. It can be seen that the experimental waveforms have similar characteristics to the simulation results and behave appropriately.

    Both the experimental and simulation results show that the ripple of the converter-side current varies with the circuit topology and the parameters of the input filters, but the harmonics of the grid-side current are not significantly different in all four cases. It can be seen that the low-order harmonics, which have a significant impact on the grid-side current quality, are sufficiently suppressed by the current controller.

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    Figure 8. Experimental and simulation waveforms.

    Table 10 shows the design values and experimental results of the current ripple, temperature rise, and THD of the grid current. For these metrics, only results at a rated load are compared, as their maximum values are considered during the design phase. The current ripple is similar to the design value for the 2L converter, while the 3L-NPC converter shows more deviation from the design value. In the 3L-NPC converter, the parasitic inductance along the switching path is larger due to the increase in the number of power semiconductor devices and the complexity of the busbar structure of the PCB, and the voltage spikes generated during switching have the effect of making the current ripple larger.

    The THD of the grid-side current is not considered in the design tool introduced in this paper, but the measured current THD is shown to confirm that the input filter, considering only the converter-side ripple current, can keep the current THD low enough if a sufficiently good PR controller is used under a fast switching frequency. The temperature rise was calculated by measuring the temperature of the heatsink near where the power semiconductor is attached, as shown in Figure 7. In the model in Figure 6, the power semiconductor losses were calculated as Ploss and compared to Theatsink’s calculations and measurements.

    The heatsink model was calculated with a simple concentrated integer thermal resistance, and the temperature of three heatsinks near the power semiconductor was measured and averaged. For the 2L converter, the temperature rise difference between the design and experimental results is smaller, but for the 3L-NPC converter, the deviation is relatively larger. In the case of the 2L converter, the number of semiconductor devices and the size of the heat sink are smaller, so the heat transfer structure is simpler and more in line with the simple model in Figure 6, but in the case of the 3L-NPC converter, the placement structure of the power semiconductor devices and the heatsink is relatively more complex, which is estimated to cause a slight deviation from the model.

    Table 10. Current ripple, THD, and temperature rise of design value and experimental results.

    Figure 9 shows the calculated efficiency of the design tool and the measured efficiency from the experiment. The losses in the power semiconductor and the losses in the input filter were used to calculate the efficiency. Overall, the deviation between the measured and calculated efficiency at low loads is large, and the error decreases as the load factor increases.

    At light loads, the iron losses in the input filter account for a large portion of the total losses, and it is assumed that the iron losses calculated through (12) are different from the actual losses incurred, leading to the error. The flux density is used as an input variable to calculate the iron loss in Equation (12). In the proposed design tool, the flux density is derived based on the maximum value of the current ripple calculated in (2).

    However, in practice, the magnitude of the current ripple varies with the phase angle [28]. In the phase section where the current ripple is reduced, the flux density is also reduced, resulting in smaller iron losses. As a result, the calculated value of iron loss is larger than the actual value. Further improvements in flux density variation according to phase angle may be needed to increase the precision of the iron loss calculation. However, as a tool used in the basic design phase of a converter, it can be considered to have a reasonable calculation error. It is also appropriate that the calculation error is reduced under heavy loads, as efficiency at higher load factors is generally considered more important.

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    Figure 9. Efficiencies vs. loads of design value and experimental results.

    5. Conclusions

    This paper presents a design tool for designing three-phase grid-connected AC–DC converters. The basic design procedures for drafting the system design of a 2L or 3L-NPC converter were introduced, and the theory and formulas used in each design procedure were presented. The introduced design tools view the converter as an electrical circuit composed of lumped elements and set basic specifications, such as the input and output voltages, capacitance, converter topology, and limit conditions, such as the efficiency, voltage and current ripple, and temperature rise, and select switching elements.

    Based on the input parameters, the ripple of the input current, DC-link voltage, and current ripple are calculated to derive the electrical parameters of the input filter and DC-link capacitor, and the converter losses and temperature rise are calculated to verify that the limit conditions are met.

    The input filter uses the LCL filter structure, which is widely used in grid-connected converters. To limit the converter-side ripple current, the converter-side inductor value is determined first, and the grid-side inductor value is set accordingly. The capacitor value is determined according to the user-entered reactive power magnitude limit, and the damping resistor value is set to make the impedance of the input filter at the resonant frequency large enough.

    Then, to calculate the efficiency, the converter losses are calculated. There are two main types of losses discussed in this paper: power semiconductor losses and input filter losses. The power semiconductor losses are calculated using the device’s datasheet information. The rms and average current flowing in each device are calculated and applied to the datasheet information of the power semiconductor device to calculate the conduction and switching losses.

    The temperature rise is calculated using the thermal resistance information of the semiconductor device, the heatsink, and the previously calculated losses of the semiconductor device. The losses of the input filter are calculated by calculating the copper and iron losses of the inductor.

    The current ripple in the DC stage is calculated analytically using the given system specifications and operating conditions. The calculated current ripple is used to find the minimum value of the DC-link capacitor that satisfies the voltage ripple given as a limit.

    Using the introduced design tool, the converter design for various conditions is carried out and validated through a simulation and experiment. For four 10kVA-class converters, the design tool was used to derive the parameters of the input filter and the minimum value of the DC-link capacitor, and simulation models and prototypes were built based on the derived values and compared with the results of the design tool.

    The experimental results showed that the temperature rise and current ripple magnitude were similar to the results of the design tool. The measured efficiency showed some deviation from the calculated value in the light-load region, but overall, the trend of efficiency change with load factor was similar in the design value and the experimental result, and the difference in the absolute values was small, showing that it is suitable as a basic design tool.

    Authors

    Myoungho Kim, Hyeok-Jin Yun

    Original – MDPI

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  • A New Design Technique for a High-Speed and High dVdt Immunity Floating-Voltage Level Shifter

    A New Design Technique for a High-Speed and High dV/dt Immunity Floating-Voltage Level Shifter

    20 Min Read

    Abstract

    This paper presents a high-speed level shifter with about 500 V/ns power supply slew immunity. In this designed structure, a narrow pulse-controlled current source is adapted to accelerate the voltage conversion and reduce the power consumption. A Fast-Slewing Circuit speeds up the operation of the level shifter based on the current comparison principle.

    Edge detection technology is used to filter the generated voltage noise and achieve high dV/dt immunity. The proposed level shifter simulated with the 0.18 μm BCD (bipolar-CMOS-DMOS) process shows fast responses with a typical delay of 1.49 ns and 500 V/ns dV/dt immunity in the 200 V high-voltage application, which only occupies a 0.022 mm2 active area with the 0.18 μm BCD process.

    1. Introduction

    In recent years, the continuous growing markets in 5G communications, wireless transmission, fast charging industries, etc., create a huge demand for advancing today’s high-voltage (HV) power converters for cost and energy savings. Silicon-based power semiconductor devices have reached their physical limits due to their restrictions on device size and their physical characteristics. Although the switching losses in power devices can be reduced by applying technologies like soft switching, the large gate parasitic capacitance of silicon-based devices limits the optimization of energy loss, which affects the performance of power converters under high-input-voltage and high-frequency conditions [1].

    Wide-bandgap (WBG) semiconductor materials, such as silicon carbide (SiC) and gallium nitride (GaN), have been demonstrated to offer excellent features compared to silicon. For instance, wide-bandgap (WBG) semiconductor materials allow smaller, faster, more reliable power electronic components than their silicon-based counterparts [2]. The wide-bandgap power devices exhibit greater thermal conductivity and electric field strengths, and as a result, SiC and GaN power devices have lower on-resistance to reduce conduction losses [3].

    Therefore, the wide-bandgap GaN and SiC devices have gradually replaced the original silicon-based power semiconductor devices for their excellent performance advantages, producing a technological revolution in the fields of information communication, electric vehicles, and consumer electronics [4,5,6,7].

    Usually, SiC and GaN power devices are used in half-bridge drivers as power switches. Level shifters are commonly employed as a transmission bridge between different voltage domains to shift the potential of the control logic from the low-voltage domain to the high-voltage domain or from the high-voltage domain to the low-voltage domain [8]. The high-voltage domain mainly includes level shift, high-side drive, and bootstrap circuits.

    Unlike the supply voltage of the low-voltage domain (usually a fixed voltage below 5 V), the high-voltage domain is powered by floating power rails (VDDH and VSSH). When the high-side power transistor is turned on, the low-voltage VSSH of the floating power rail is approximately equal to the input voltage VHV of the half-bridge driver, and the high-voltage VDDH of the floating power rail is equal to VSSH + VCC.

    To turn on and off the high-side power transistor, the high-side driver needs to run on a floating power rail. The logic control signal is from the low-voltage domain and must be transformed to a high-voltage domain logic signal. As shown in Figure 1, the low-voltage control signal is sent to the level shifter after going via the Input Detection module, which activates or deactivates the high-side power transistor.

    Therefore, as a bridge connecting the high-voltage domain and the low-voltage domain, the level shifter is one of the most critical circuits in the half-bridge driver. However, the GaN and SiC MOSFET can generate larger dV/dt and di/dt noise in the fast switching. For GaN MOSFET, the dV/dt could be up to above 200 V/ns [9]. This fast slewing is particularly problematic on the high side of the half-bridge driver, as shown in Figure 1.

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    Figure 1. The block diagram of the GaN high-voltage half-bridge driver.

    Figure 2 shows the reliability issues with traditional GaN drivers. When the high-side power transistor is activated, the voltage of VSSH will be quickly raised to VHV, and the rising speed is >200 V/ns. This dVSSH/dt change is coupled to the level shifter through a bootstrap capacitor. Since the level shifter can perform voltage conversion between the low-voltage domain and the high-voltage domain, MH1 and MH2 are high-voltage transistors, whose parasitic capacitance is large.

    The parasitic capacitance will generate a charging or discharging current when dV/dt happens, which will interfere with the level shifter’s normal operation and cause errors in the driver’s logic voltage of the high-voltage domain [10,11,12]. In Figure 2, it can be seen that under the action of the bootstrap capacitor CBOOT, VDDH changes with VSSH, and dVDDH/dt is approximately equal to dVSSH/dt. However, since the input MOS device MH1 of the level shifter is a high-voltage transistor, there is a large parasitic capacitance Cpar at node A.

    The rapid change of the VDDH acts on Cpar to generate a large current, which pulls down the voltage of node A. When the noise amplitude (=R × Cpar × dVSSH/dt) generated at node A is larger than (VBOOT − VT), the recovery circuit of the subsequent stage may transmit the noise signal by mistake, where VBOOT is equal to VDDH − VSSH. Therefore, the dV/dt immunity capability of the driver is limited by the parasitic capacitance of the HV transistor of the level shifter.

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    Figure 2. Reliability problem of the traditional level shifter.

    Existing high-voltage level shifters have employed a number of design techniques to improve dV/dt immunity [13,14,15]. In [13], the author proposed a level shifter based on high-bandwidth current and latch structure; the delay is 370 ps, but the dV/dt slew immunity is only 30 V/ns. Yang et al. adopted a new technique to enhance the slew rate of level shifters, achieving a novel level shifter with 120 V/ns immunity and 20 ns propagation delay [14].

    The level shifter (LS) proposed in [15] is designed with a current mirror/latch structure, and a common-mode noise canceller is also applied to enhance the dV/dt immunity. This level shifter achieves 200 V/ns noise immunity and sub-nanosecond delay in the SOI process, but this good performance is limited by the process. As the supply voltage increases, level shifters made with traditional processes suffer more from dV/dt noise. Then the ensuing problem is that the level shifter needs to consume more energy to enhance the dV/dt immunity of the circuit. As a result, several conventional structures designed to enhance the dV/dt noise immunity of the level shifters become inappropriate as the power supply voltage rises.

    This paper presents a high-speed and high dV/dt immunity floating-voltage level shifter in the 0.18 μm BCD process. The proposed design can achieve a small propagation delay and an ultra-high dV/dt noise shielding function.

    The rest of this paper is organized as follows: In Section 2, two conventional level shifter designs are reviewed. In Section 3, a novel enhanced level shifter is proposed, and its propagation delay and dV/dt immunity are analyzed in detail. Section 4 and Section 5, respectively, display the simulation results and conclusion.

    2. Previous Level Shifter

    A conventional level shifter is shown in Figure 3 [16]. The MOS transistors M1–M4 are high-voltage transistors. LDNMOS (laterally diffused N type metal oxide semiconductor) transistors M1 and M2 connect their gates to VDDL to protect and clamp the low-voltage (LV) transistors ML1 and ML2. In addition, the circuit connects the gates of the LDPMOS (laterally diffused P type metal oxide semiconductor) transistors M3 and M4 to VSSH to protect the low-voltage transistors ML5 and ML6 from being damaged by breakdown.

    This circuit can convert the low-voltage power rail signal from GND-VDDL to the high-voltage floating power rail signal VSSH-VDDH. However, LDNMOS and LDPMOS transistors increase the parasitic capacitance and cause large propagation delays. More seriously, this structure suffers from mismatch delay and low dV/dt noise immunity. This level shifter has inconsistent low-to-high and high-to-low conduction delays due to the current asymmetry between the rising and falling edges of the output node.

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    Figure 3. Traditional level shifter based on high-voltage PMOS clamping.

    Figure 4 shows another type of conventional level shifter [17]. This topology clamps the voltage at nodes N1 and N2 to VDDH − VGS by using the diode-connected low-voltage PMOS transistors M1 and M4, where VGS is the gate-source voltage of the PMOS transistors. When the input signal VIN switches from low to high, the high-voltage tube LDNMOS1 is turned on; then the potential of the N1 point is pulled down, and the potential of the N2 point rises.

    However, the potential at point N1 decreases more slowly than the potential at point N2 rises due to the current asymmetry. In the same way, when the VIN switches from high to low, the high-voltage tube LDNMOS2 is turned on; then the potential of the N2 point is pulled down, and the potential of the N1 point rises. The falling speed of the potential at point N2 is slower than the rising speed at point N1. For the structure in Figure 4, only a pair of high-voltage transistors, LDNMOS1 and LDNMOS2, are used, which has a lower parasitic capacitance than the structure in Figure 3. However, this level shifter faces the same difficulties as the structure shown in Figure 3, namely, that there is a severe mismatch delay and low dV/dt noise immunity.

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    Figure 4. Traditional level shifter based on diode-connected PMOS clamping.

    3. Proposed Enhanced Level Shifter

    As shown Figure 5, this paper presents a high-speed and high dV/dt immunity level shifter which consists of three parts: the Power Supply Rail Conversion Circuit, the Fast-Slewing Circuit (FSC), and the dV/dt Noise Shielding Circuit. The Power Supply Rail Conversion Circuit converts the signal from the low-voltage domain to the high-voltage domain. The Fast-Slewing Circuit speeds up the level shifter’s signal conversion. And then the dV/dt Noise Shielding Circuit can shield the dV/dt noise to make the output of the level shifter remain constant.

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    Figure 5. Top structure and strategy of the proposed level shifter.

    In Figure 5, the input transistors M1 and M2 are low-voltage MOS devices. The diode-connected transistors M7 and M8 are used to clamp the voltages of node A and node B. The gate of the high-voltage transistors MNLD3 and MNLD4 are connected to the low-voltage rail power supply VDDL to bear high voltage, preventing the breakdown of the low-voltage transistors M1 and M2. The M5 and M6 transistors are used in the form of diodes, with their sources connected to the floating power supply ground VSSH to ensure that the voltages of node A and node B can be higher than VSSH − VTH (VTH is the threshold voltage of the MOSFET).

    This prevents the drain-source voltage of the M7 and M8 devices from exceeding the safe voltage range. A narrow pulse generation circuit is adopted to generate the instantaneous driving signal and speed up the operation of the level shifter [18]. Additionally, the Fast-Slewing Circuit that was added to the circuit can speed up the voltage conversion rate of the level shifter even more, eliminating the issue of various mismatch delays.

    The problem of dV/dt immunity is the most important concern of the level shifter, which can be analyzed from the two situations of positive swing and negative swing of the power supply. As shown in Figure 6, when the VIN is high, the normal states of VA − VSSH and VB − VSSH are low voltage and high voltage, respectively. When VSSH and VDDH quickly transition from high voltage to low voltage, both VA − VSSH and VB − VSSH rise to high voltage.

    When VSSH and VDDH transition from low voltage to high voltage, both VA − VSSH and VB − VSSH can drop to low voltage. Therefore, the dV/dt Noise Shielding Circuit is meant to maintain the level shifter’s output in order to avoid the succeeding stage circuit from receiving the erroneous signal output of the level shifter.

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    Figure 6. Noise shielding feature for dV/dt when the VIN is high.

    3.1. Strategy for the Enhanced Level Shifter

    The level shifter proposed in this article is shown in Figure 7. The signal conversion of the level shifter can be sped up by using the Fast-Slewing Circuit and the double-pulse generation circuit. The double-pulse generation circuit can generate a voltage pulse on the rising and falling edges of an input signal, consisting of a NAND gate, a capacitor, and several inverters. In the proposed level shifter, the input of this double-pulse generation circuit is the signal of the VIN, and the output of the circuit is used to control the on and off of M1 and M2.

    Therefore, whenever there is a conversion of high voltage to low voltage or low voltage to high voltage, a large current will appear in the voltage conversion branch, improving the voltage conversion speed. At the same time, the transistors M1 and M2 are turned off during the voltage holding stage, so that the level shifter has very low static power consumption.

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    Figure 7. Schematic of the proposed level shifter circuit.

    The Fast-Slewing Circuit is a current mirror that makes use of the principle of current comparison to achieve rapid voltage conversion speed [19]. As can be seen in Figure 7, when the VIN signal transitions from low voltage to high voltage, the voltage of node A can drop rapidly with the help of the huge pull-down capability of the transistor M1, while the asymmetric current of the circuit causes the voltage of node B to rise slowly.

    Therefore, the proposed level shifter adopts the Fast-Slewing Circuit to improve the response speed. The voltages at nodes A and B are mirrored to nodes D and C through a current mirror, respectively, after passing through the Fast-Slewing Circuit, preventing the circuit from various mismatch delays. Then, the rising edge of node C or D can be captured by the edge detection circuit and locked by the SR latch, which finally changes the output of the level shifter and keeps it constant until the VIN changes.

    3.2. The Propagation Delay of the Proposed Level Shifter

    The proposed level shifter’s operation for switching from low to high is shown in Figure 8a. Before the VIN becomes high, VA is equal to VDDH, and VB is equal to VSSH. The signal transmission process of the level shifter is as follows:

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    Electronics 12 04841 g008b

    Figure 8. The suggested level shifter’s switching operation: (a) low-to-high switching operation; (b) high-to-low switching operation.(1)

    When the VIN changes from low voltage to high voltage, the generation circuit, which consists of a NAND gate, a capacitor, and several inverters, generates a voltage pulse on the rising edges of the VIN signal. The delay in this process is called Tr0, which is determined by the delay of the NAND gate.(2)

    When the voltage pulse generates, the input transistor M1 is turned on, and the voltage VA at node A begins to drop rapidly. The delay in this process is called Tr1. The strong pull-down capability of M1 will briefly provide a large current to the branch where node A is located to increase the response speed of node A.(3)

    The current M7 is mirrored by the M9. Due to the small current of M10, the current of M9 is much greater than that of M10, so the potential at node C is rapidly raised to VDDH. The Tr2 is the transmission delay from node A to node C, which is determined by the delay of the current comparator.(4)

    The edge detection circuit can identify the rising edge signal of node C. When VC becomes high, a short pulse signal is generated at node S under the action of the delay chain composed of INV1-INV3 and NAND1. Tr3 is the delay of the edge detection circuit.(5)

    The generation of a short pulse signal VS triggers the flipping voltage of NAND4. At this point, the VOUT transitions from low to high and remains at VDDH until a short pulse occurs at node R. The delay between VS and VOUT is described by Tr4, which is the delay of NAND4.

    The current of M7 can also be mirrored to M15 through M13 and M14. Due to the small current of M16, the voltage at node D is quickly pulled down. Although the descent speed of VD is slower than the ascent speed of VA, the drop of VD is not detected by the edge detection circuit and is just prepared for the next reset. Therefore, when the input signal VIN changes from low to high, the speed at which the voltage at node D changes has no effect on the circuit.

    As shown in Figure 8b, when the input voltage of the level shifter transitions from high to low, the propagation delay Td_f of the signal consists ofTf0, Tf1, Tf2, Tf3, Tf4, Tf5, and Tf6. Due to the good symmetry of the proposed level shifter, Tr0 is equal to Tf1, Tr1 is equal to Tf2, Tr2 is equal to Tf3, Tr3 is equal to Tf4, and Tr4 is equal to Tf5. Therefore, it can be seen that Td_f has two more delay items, Tf0 and Tf6, than Td_r, which are the delays of the two NAND gates. Therefore, Td_r is smaller than Td_f.

    3.3. The dV/dt Immunity of the Proposed Level Shifter

    The edge generation circuit of the proposed level shifter has two functions. One is that the edge generation circuit can output a pulse signal at the rising edge and falling edge of the input signal; on the other hand, the edge generation circuit generates a large current during the narrow pulse signal to help the signal transfer quickly, and reduces the overall power consumption of the circuit by turning off the input transistors M1 and M2 during the VIN signal hold.

    The transient operation of the proposed level shifter is demonstrated with low-to-high and high-to-low operations. When the VIN shifts from low to high, M1 is activated and M2 is turned off. The voltage at node A starts declining, the dropping edge of node A is sampled, and the rise of node C is accelerated by the current comparison circuit. The rising edge of node C is delayed by the delay circuit composed of the inverters INV1–INV3, and then the delayed signal is input to NAND1 together with the signal of node C. Next, a low-voltage pulse signal S is generated, and then the voltage of the VOUT changes from low to high.

    When the input signal VIN changes from high to low, M2 is turned on, and M1 is turned off. The voltage at node B begins to drop, and then the falling edge of node B is sampled, which speeds up the rising speed of node D. The rising edge of node D can be delayed by the inverters INV4–INV6 and this delayed waveform is input into NAND2 with node D. At this time, a low-level pulse is generated in R to make the VOUT change from high to low. Figure 9 shows the waveform of the level shifter during the VIN transient changes.

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    Figure 9. The waveform of the level shifter during VIN transient changes.

    The proposed level shifter can shield dV/dt noise by using the dV/dt Noise Shielding Circuit, which consists of INV1–INV6 and NAND1, NAND2. The voltages at nodes C and D will rise or fall synchronously when dV/dt noise is generated due to rapid changes in the VSSH and VDDH. If the dV/dt noise is high, voltage changes at nodes C and D may trigger the logic gates of the edge detection circuit. Positive dV/dt noise will cause undershoot voltage at nodes C and D, and negative dV/dt noise will cause overshoot at nodes C and D.

    However, these generated voltage noises will be filtered after passing through the edge detection circuit, so that no error signals will be generated at the S and R terminals, and the state of the RS latch will not be changed. Therefore, the proposed level shifter can shield the dV/dt noise from disturbing the output VOUT, so that the VOUT can remain constant.

    4. Simulation Results

    The proposed level shifter is simulated at the 0.18 μm BCD process using the Cadence Virtuoso tool. Figure 10 shows the simulated propagation performance of the proposed level shifter with 205 V VDDH and 200 V VSSH under the typical process corner. All power rails are supplied with fixed voltage sources during simulation (VDDH − VSSH = 5 V, VDDL = 5 V). The VIN is operated under 5 V supply voltage, and the low voltage of the VOUT is 200 V and the high voltage is 205 V.

    It can be seen from Figure 10 that when the rising edge of the VIN is generated, the voltage at node A drops and triggers the low-voltage pulse signal of the S terminal of the RS flip-flop, and then the VOUT starts to flip from low to high. The voltage at node B decreases when the falling edge of the VIN arrives; then the R terminal of the RS flip-flop generates a low-voltage pulse signal, and the VOUT starts to change from high to low. The simulation results show that the propagation delay of the rising edge is about 1.23 ns, and the propagation delay of the falling edge is about 1.75 ns.

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    Figure 10. Propagation delay of the proposed level shifter.

    Figure 11a,b show the rising and falling delays of the proposed level shifter under three process corners, ss (Worst Case), tt (Typical Case), and ff (Best Case), at temperatures −55 °C and 150 °C. The simulation results show that the minimum rising delay is 479 ps and the maximum is 2.64 ns; the minimum falling delay is 842.1 ps and the maximum is 3.4 ns.

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    Figure 11. Simulation results of the proposed level shifter’s delay: (a) rising delay; (b) falling delay.

    Figure 12 simulates the dV/dt noise shielding function of the proposed level shifter at ±500 V/ns dV/dt noise. The simulation results show that when dV/dt noise is generated, the voltages VS and VR have no erroneous logic signals during the period when the input signal VIN is high, the output signal VOUT is not disturbed by dV/dt noise, and the state remains unchanged.

    Therefore, this can demonstrate that the level shifter proposed in this paper can achieve ±500 V/ns dV/dt immunity, which is also suitable for other supply voltages and processes. Figure 13 shows the layout of the proposed level shifter. The chip area is only 127 μm × 178 μm at the 0.18 μm BCD process.

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    Figure 12. Simulation results of the dV/dt noise shielding function of the proposed level shifter.

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    Figure 13. The layout of the proposed level shifter.

    Table 1 shows the performance comparison between the proposed level shifter and previous reported level shifters. FOM is used to evaluate the performance of the level shifter by combining delay, supply voltage, and process node. It can be seen from Table 1 that the high-voltage level shifter proposed in this paper has the highest dV/dt immunity and the smallest FOM. Therefore, the proposed level shifter can still achieve sufficient response speed and high reliability under a 200 V power supply.

    Table 1. Comparison with previous work.

    5. Conclusions

    This paper presents a high-voltage level shifter for a GaN half-bridge driver that offers high-speed operation and high dV/dt immunity. A narrow pulse-controlled current source and the Fast-Slewing Circuit speed up the transmission of the level shifter and reduce the power consumption. Edge detection technology is utilized to filter the generated voltage noise and then achieve the ultra-high dV/dt immunity of the level shifter without using complex auxiliary circuits.

    In the 0.18 μm BCD process, the proposed level shifter can achieve a propagation delay of 1.49 ns and a 500 V/ns dV/dt immunity under a 200 V power supply, which only occupies a 0.022 mm2 active area. The FOM is very small, which is only 0.041. The suggested level shifter can be utilized in multi-MHz converters because of its low propagation delay and its ability to provide 500 V/ns of slewing immunity, making it suitable for drivers of wide-bandgap power device applications.

    Authors

    Min Guo, Lixin Wang, Shixin Wang, Yuan Zhao and Bowang Li

    Original – MDPI

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  • Influence of JFET Width on Short-Circuit Robustness of 1200 V SiC Power MOSFETs

    Influence of JFET Width on Short-Circuit Robustness of 1200V SiC Power MOSFETs

    25 Min Read

    Abstract

    This paper investigates and compares the static performance and short-circuit (SC) robustness of 1200 V SiC MOSFETs with varying JFET widths (WJFET = 2.0–5.0 μm). Short-circuit measurements as well as electrical-thermal simulations are used to identify thermal distribution and maximum electrical field, providing valuable insights into the design limits. The devices under test (DUTs) with narrow and wide WJFET exhibit different failure mechanisms under SC stress.

    After the short-circuit failure, interlayer dielectric (ILD) cracks are observed in DUTs with narrow JFET width (WJFET < 3 μm). In contrast, it is discovered that the burn mark is located in the channel region of the device with a wide JFET width. Moreover, the short-circuit withstand time (SCWT) of DUTs with narrow and wide WJFET exhibits varying trends under high temperature conditions (100 °C). These results can help verify the different failure mechanisms and determine an optimal JFET design to improve the trade-off between the static performance and SC ruggedness of the SiC MOSFETs.

    1. Introduction

    SiC MOSFETs have already emerged as one of the most crucial components in power electronic systems. They can be utilized at frequencies exceeding 100 kHz, which can facilitate a reduction in the volume of passive components and enhance the power density of the system [1]. MOSFETs are gaining increasing popularity in electric vehicles (EVs), hybrid electric vehicles (HEVs), and railways, with a growing interest in their reliability and robustness.

    Approximately 38% of inverter failures can be attributed to the failure of power devices induced by short-circuit (SC) stresses [2,3,4]. During the device operation, unexpected circuit faults may occur. For example, in the half-bridge circuit, failures often arise from short circuits in the upper or lower bridge devices, and the device channel may accidentally conduct current when the device withstands the high drain voltage. This high current density flowing through the device can lead to device failure.

    Numerous investigations have been conducted on the short-circuit characteristics of commercial SiC MOSFETs. The results of the short-circuit test provide valuable information about the SiC MOSFET’s ability to handle short-circuit faults without suffering permanent damage. It helps in determining the device’s short-circuit withstand capability, evaluating the effectiveness of its protection mechanisms, and assessing its thermal management strategies [5].

    This knowledge is crucial for designing reliable power electronic systems that utilize SiC MOSFETs and ensuring their safe operation under various fault conditions. The short-circuit performance of SiC MOSFET power modules under various operating conditions has also been studied [6,7]. Compared to Si IGBTs, the short-circuit withstand time (SCWT) of SiC MOSFETs is 80% shorter due to their larger current densities and higher electrical fields [7]. During the short-circuit (SC) process, the heat generated in SiC MOSFETs leads to a rapid increase in the junction temperature, exceeding 1000 °C [8,9].

    The rapid increase in junction temperature induces thermal and mechanical stress on the interface between aluminum and the interlayer dielectric. This stress has been observed to cause cracks at the corner of the interlayer dielectric, as reported in references [10,11]. The oxide thickness, Pwell doping and channel length have been extensively studied in SiC MOSFETs [12,13,14]. Channel structure on the short-circuit capability of SiC MOSFETs has been investigated. The impacts of channel design parameters, such as doping profiles and dimensions, are compared, offering guidelines for optimizing the channel structure for enhanced short-circuit performance [15].

    The impacts of gate structure on the short-circuit performance of SiC MOSFETs are explored. Different gate designs influence the device’s ability to handle short-circuit events, providing insights into optimizing the gate structure for improved short-circuit withstand time [16]. However, the short-circuit robustness of SiC MOSFET with different JFET widths and the optimal design for JFET width are still under investigation. JFET width is the vital parameter in SiC MOSFET, which not only affects the on-resistance, electrical field at oxide, but also influences the saturate current and short-circuit characteristics.

    The device researcher always focuses on the optimal parameters in static performance, but the comparison of short-circuit characteristics of switches with different JFET widths needs to be evaluated. Furthermore, devices from various manufacturers have different value (Commercial device of A company has the width of 1.75 μm. Commercial device of B company has the width of 2.8 μm).

    In this study, SiC MOSFETs with various structural parameters are fabricated and their impacts on short-circuit capability are investigated. The correlation between short-circuit withstanding time and measurement temperature is studied. Electrical-thermal simulations are used to identify thermal distribution and maximum electrical field, providing valuable insights into the design limits. Additionally, device failure mechanisms are analyzed based on experimental and simulation results for different structure designs. Finally, the optimal structure design of SiC MOSFETs is summarized for improving the trade-off relationship between device conduction performance and short-circuit ruggedness.

    2. Materials and Methods

    2.1. Static Characteristics of SiC MOSFETs with Different Structural Parameters

    As shown in Figure 1, the JFET width (WJFET) is one of the key structural parameters for SiC MOSFETs, which significantly affects both device performance and reliability. To study its impact on short-circuit ruggedness, 1200 V SiC MOSFETs with various WJFET (2.0, 2.5, 3.0, 4.0, and 5.0 μm) are fabricated in this work. In the fabricated SiC MOSFETs, the channel doping is 1 × 1017 cm−3, the drift region doping is 8 × 1015 cm−3 and the drift thickness is 12 μm. The fabrication flow is shown in Figure 2. In SiC MOSFET, the JFET region is located between two adjacent P well regions.

    And P well—Nepi—P well is like JFET (junction field effect transistor), so this region is named the JFET region. Due to the intrinsic depletion region, the real current path is narrower than the dimension of WJFET. To optimize, the minimal resistance and minimize electrical field are at the center of gate oxide (<3 MV/cm).

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    Figure 1. The schematic diagram of the 1200 V SiC MOSFET.

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    Figure 2. Manufacture flow of the 1200 V SiC MOSFET.

    The five SiC MOSFET devices in this study are labeled A1–A5. The devices have identical active areas and chip sizes. In this section, the static characteristics of the five MOSFET devices are measured and analyzed.

    The transfer, output and blocking I–V (current-voltage) characteristics of the five devices are measured by Keysight B1505A equipment and the results are compared in Figure 3. For the transfer I–V characteristics, the drain-source voltage (VDS) is set to 10 V in the measurement. For the output I–V characteristics, the gate-source voltage (VGS) is set to 20 V. For the blocking I–V characteristics, the VGS is set to 0 V. Device performance indexes, such as threshold voltage, resistance, transconductance and breakdown voltage are extracted and summarized in Table 1.

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    Figure 3. Static characteristics of SiC MOSFETs with different JFET widths.

    Table 1. Static characteristics of SiC MOSFETs with different JFET widths.

    With increasing WJFET design, the threshold voltage initially decreases from 2.58 to 2.52 V, and then increases to 2.73 V. Correspondingly, the on-resistance decreases from 1.68 to 1.48 Ω, and then increases to 1.6 Ω. The transconductance of the device gradually increases from 0.377 to 0.841 S. Besides, from the blocking characteristics, all five devices can successfully achieve blocking voltages above 1700 V.

    The on-resistance of a SiC MOSFET device is composed of channel resistance, JFET region resistance, drift layer resistance and substrate resistance. For 1200 V SiC MOSFETs, JFET region resistance contributes around 30% of the total resistance at room temperature. Increasing the WJFET can help reduce the JFET region resistance. However, it can also result in an increase in the cell pitch and a decrease in channel density, if the source region width remains constant. According to the experimental results, Device A3 with WJFET = 3 μm achieves the lowest resistance of 1.48 Ω among the five designs.

    The output characteristics of the five devices are measured at 25 to 175 °C to investigate the conduction performance of SiC MOSFETs at high temperatures. The on-resistances at different temperatures are presented in Figure 4. It can be observed that the on-resistance increases with temperature for all five devices, but the temperature coefficient of resistance varies for different WJFET designs.

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    Figure 4. (a) Compositional channel resistance and total resistance at elevated temperature. (b) Compositional resistance in Device A1.

    The channel resistance of VDMOS is determined by calculating the resistance of lateral long channel MOSFET and converting it based on channel length and width, as seen in Figure 4. The channel resistance accounts for more than 30% of the total resistance. The channel resistance decreases as the temperature increases from room temperature to 175 °C. At higher temperatures, the threshold voltage of the device decreases, resulting in an increased generation of electrons in the channel. Furthermore, higher electron densities in the channel provide a better screening effect, reducing the Coulomb scattering caused by interface traps.

    These two factors contribute to the overall reduction in channel resistance [12]. Apart from the channel resistance, the bulk resistance exhibits a positive temperature coefficient, which is due to the lower mobility of carries at elevated temperatures caused by acoustic scattering. The opposite temperature behaviors of the channel resistance and bulk resistance components lead to the different trends in total resistance at elevated temperatures for devices with different WJFET. With a narrower JFET width, the JFET resistance becomes a larger proportion of the total resistance. Consequently, the total resistance increases more rapidly at elevated temperatures.

    For Device A1, with a narrow WJFET design (2.0 μm), the JFET region resistance contributes significantly to the total on-resistance. It also has a positive temperature coefficient, resulting in the highest slope among the five devices in Figure 3. For Device A5, with a wide WJFET design (5.0 μm), the JFET region resistance contributes only a small portion to the total on-resistance. In contrast, the channel resistance plays a more significant role in determining the overall resistance of Device A5.

    The negative temperature coefficient of the channel resistance in Device A5 counterbalances the positive temperature coefficient of JFET region resistance, drift layer resistance and substrate resistance. Thus, the slope of the curve for Device A5 in Figure 3 is the lowest among the five devices. For Device A3 to A5, the on-resistances are less sensitive to ambient temperature, which is good for high temperature applications. The slight increase in on-resistance with temperature is beneficial for balancing current in parallel connections.

    The devices’resistance types are channel resistance, JFET resistance, drift resistance and substrate resistance, as shown in Figure 4, and the resistance is mainly based. To illustrate the reason for the transconductance and on-resistance exhibiting different trends, the different compositional resistance needs to be separated, as shown in Figure 4b. Transconductance is mainly controlled by channel resistance, as the channel resistance is dependent on the gate voltage. If the channel resistance occupies a larger portion in the on-resistance, the transconductance is higher. In five types of DUTs, the wider WJFET has a larger portion of channel resistance, so the transconductance is higher.

    WJFET influence the cell pitch and also have a large impact on JFET resistance. When WJFET decreases, smaller cell pith results in the reduced channel resistance. However, narrower WJFET leads to increased JFET resistance, which is a trade-off in different devices. Among five types of devices, the WJFET = 3 μm is the optimal value.

    2.2. Short-Circuit Capability of SiC MOSFETs

    A short-circuit (SC) test platform has been established. Figure 5a illustrates the test bench, while Figure 5b presents the schematic diagram of the test board. The device under test (DUT) is connected in series with an IGBT device and a current shunt. A pulsed gate-source voltage is applied to the gate terminal of the DUT, and the duration of the short circuit is controlled by the pulse width. The duration of the short-circuit time gradually increased until the device reaches a failure state. In this section, we compare the short-circuit withstand time (SCWT) of SiC MOSFETs with different WJFET designs. We also analyze the device failure mechanisms, considering various device designs and different bus voltages.

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    Figure 5. (a) Short-circuit test bench. (b) Schematic diagram of the SC test board.

    3. Results

    3.1. Short-Circuit Capability of SiC MOSFETs with Different JFET Widths at 400 V

    The on and off gate-source voltages (VGS) are 20 and −5 V, respectively. The bus voltage is 400 V, and the short-circuit duration time is increased with a step of 0.5 μs until the device fails. The last non-destruction short-circuit current waveforms for different device designs are illustrated in Figure 6a. According to the figure, the SCWT of Device A1, A2, A3, A4, and A5 are 19.0, 18.5, 17.0, 15.0 and 14.0 μs, respectively. Device A3 with WJFET = 3.0 μm demonstrates the highest peak current due to the lowest on-resistance, as discussed in Section 2.

    On the other hand, the SCWT gradually decreases with the increase in WJFET. The changes in peak current and SCWT with WJFET are summarized in Figure 6b. The typical waveform of gate voltage and drain current for the destruction test are shown in Figure 6c. After the destruction test, it is observed that the gate is shorted to the source terminal for all five devices. When the WJFET is increased from 2.0 to 3.0 μm, devices with wider WJFET exhibit higher peak currents.

    The higher peak currents result in increased energy dissipation, which can lead to a rapid rise in junction temperature and a reduction in SCWT. However, when JFET width is further increased from 3.0 to 5.0 μm, both the peak current and SCWT decrease. It is evident that wide WJFET design devices are likely to experience different failure mechanisms compared to devices with narrower WJFET designs.

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    Figure 6. (a) The SC current waveforms of five types of devices with different JFET widths at Vds = 400 V. (b) Extracted SC peak current and SCWT in devices with varied JFET widths. (c) Failure waveform including gate and drain waveforms.

    The failure mode is checked with blocking characteristic measurements after device failure, which are shown in Figure 7. After device failure, Device A2 with WJFET = 2.5 μm remains almost the same blocking voltage (Figure 7a) as a fresh device, while Device A5 with WJFET = 5.0 μm shows degraded blocking capability (Figure 7b). OBIRCH (Optical Beam Induced Resistance Change) is utilized to find out the failure spot.

    The failure spot in Device A2 is located in the active region, as shown in Figure 8a. FIB (Focus Ion Beam) analysis is employed to observe the cross-section at the failure spot. Figure 8b displays the obtained cross-sectional result of Device A2. Cracks are observed in the ILD (interlayer dielectric) between gate polysilicon and source metal in Device A2. However, for Device A5, different observations are shown. The failure spot is also observed in the active region, as shown in Figure 8c. When the device is stripped in solvents to expose the SiC layer’s surface, a burn mark is found between the JFET region and the channel region. The top view of the device is illustrated in Figure 8d.

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    Figure 7. Blocking characteristic after short-circuit failure. (a) Device A2 with WJFET = 2.5 μm. (b) Device A5 with WJFET = 5.0 μm.

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    Figure 8. (a) The hot spot is observed under OBIRCH (Optical Beam Induced Resistance Change) of Device A2 at drain voltage of 400 V. (b) The cross-section at hot spot is prepared by FIB (Focus Ion Beam) of Device A2 at drain voltage of 400 V. (c) The hot spot is observed on Device A5 at drain voltage of 400 V. (d) Top view of the failure spot of Device A5 at drain voltage of 400 V after the ILD and top metal is dissolved.

    To explain the failure mechanism, the TCAD is used to simulate the short-circuit procedure in SiC MOSFETs. The SiC/SiO2 interface mobility model is established, taking into account the presence of interface traps. The integration of the interface trap is coulomb charge named Nc. Varying the interface trap density at the SiC/SiO2 interface leads to differences in the short-circuit current waveform, as demonstrated in Figure 9a.

    With the lower interface trap density, the peak current is higher, and more heat is generated in the SiC MOSFET. The interface trap distribution is determined by extracting the interface trap from the MOS capacitance. Figure 9b shows the comparison between the simulation results (using Dit = 3 × 1011 cm−2eV−1) and the corresponding measurement results. The simulation model is established and the temperature can be extracted through the simulation.

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    Figure 9. (a) Different interface trap density is established by applying coulomb scattering considering interface trap model. (b) Comparison between measurement and simulation result by using proper model.

    For Device A2, the cracks found at ILD are due to the unmatched coefficient of thermal expansion (CTE) between different materials [17]. With higher temperatures, the CTE becomes larger [18,19]. The temperature distribution during the SC procedure at the ILD corner is calculated using a simulation tool, and the result is shown in Figure 10. Consequently, the dominant failure mechanism is the junction temperature rise caused by the energy dissipation within the device during the short-circuit pulse.

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    Figure 10. Simulated ILD and source metal temperature during the SC procedure.

    For Device A5, the failure mode could be different. To investigate the failure mode, the short-circuit transient process is simulated using TCAD. Due to the wide WJFET design, the electrical field at SiC surface (upper in JFET region) is higher than that in Device A2, resulting in a higher impact ionization. The impact ionization within Device A5 is shown in Figure 11a. Higher impact ionization leads to an increase in hole and electron current densities. A comparison of the hole and electron current densities can be seen in Figure 11b. As the electric field direction points from SiC to the gate in the JFET region, the holes would inject into the gate oxide due to the combined effect of electric field and high kinetic energy resulting from the elevated temperature.

    Additionally, in the channel region, the channel electron density in Device A5 is also higher than that in Device A2. Both the holes in the JFET region and electrons in the channel region have the potential to degrade the gate oxide and lead to device failure. To identify the main reason, a repetitive short-circuit test is conducted. The voltage shift direction indicates whether there is hole injection (negative shift) or electron injection (negative shift).

    Device A2 and Device A5 are measured during a repetitive short-circuit test with Vds = 400 V, a pulse width of 6µs and Vgs,on/Vgs,off = 19 V/−5 V. When the cycle time is low, the device with a wider JFET width is influenced more by hole injection than electron injection, as observed in the comparison of the two devices in Figure 12a. However, Device A2 is primarily affected by electron injection. With repetitive cycle increasing, the electron injection becomes dominant due to the hot electron effect, as shown in Figure 12b.

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    Figure 11. (a) Impact ionization in Device A5 WJFET = 5.0 μm. (b) Comparison of electrical field and hole current density at surface between Device A2 (WJFET = 2.5 μm) and Device A5 (WJFET = 5.0 μm).

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    Figure 12. (a) Threshold voltage shift of device with different WJFET after repetitive short-circuit test. (b) Threshold voltage shift for different short-circuit pulse widths (6 and 10 μs).

    3.2. Short-Circuit Capability of SiC MOSFETs Measured at Elevated Temperature

    Short-circuit tests are carried out at an ambient temperature of 100 °C to verify the failure mechanisms for Device A2 and Device A5. The SC current waveforms are shown in Figure 13a. The peak current and SCWT for the five WJFET designs are extracted from the figure and summarized in Figure 13b. The correlations between SC peak current (SCWT) and WJFET observed at 100 °C are similar to the results obtained at 25 °C (refer to Figure 6b).

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    Figure 13. (a) The SC current waveforms of five types of devices with different JFET widths at Vds = 400 V at elevated temperature (100 °C). (b) Extracted SC peak current and SCWT in devices with varied JFET widths at elevated temperature (100 °C).

    To study the impacts of ambient temperature on SCWT test results for different WJFET designs, the results obtained at 25 °C and 100 °C test conditions are compared in Figure 14a. The results indicate that wide WJFET designs (WJFET ≥ 3 μm) exhibit an increase in SCWT at elevated temperatures—namely, SCWT demonstrates a positive temperature coefficient for wide WJFET designs.

    The increase in SCWT can be attributed to reduced electron injection into the gate oxide at elevated temperatures. Figure 14b compares the short-circuit current waveforms for the 25 and 100 °C test conditions, with tsc = 3 μs used as an example. The peak current at 100 °C is lower than that of 25 °C due to the limitations of acoustic scattering at elevated temperatures, resulting in reduced election injection for the 100 °C test condition.

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    Figure 14. (a) Relationship between SCWT and JFET width under 25 and 100 °C. (b) Comparison of SC current at 25 and 100 °C under the SC duration time of 3 µs.

    On the other hand, for narrow WJFET designs (WJFET < 3.25 μm), SCWT decreases at elevated temperatures. The junction temperature is calculated using simulation software. Figure 15 shows the temperature distribution within the device during the short-circuit transient at both 25 °C (Figure 15a) and 100 °C (Figure 15b). Elevated ambient temperatures result in higher junction temperatures. The thermal and mechanical stress can cause cracks in ILD layers, and higher temperatures result in a larger coefficient of thermal expansion mismatch [11].

    Thus, the SCWT is decreased at elevated temperatures. In order to figure out whether failure mechanism is changed in the device with wider WJFET, failure spot of Device A4 after SC test under 100 °C is detected shown in Figure 15c. Compared with the results shown in Figure 8b, the ILD crack becomes the main failure reason for the device with wide WJFET.

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    Figure 15. Simulated ILD and source metal temperature during the SC procedure under (a) room temperature and (b) the elevated temperature. (c) The cross-section at hot spot is prepared by FIB (Focus Ion Beam) of Device A5 at drain voltage of 400 V after SC test under 100 °C.

    3.3. Short-Circuit Capability of SiC MOSFETs with Different JFET Widths at Varied Vds Measured at Room Temperature

    The SC capability of SiC MOSFETs is measured under different bus voltages (400, 600 and 800 V). The short-circuit pulse width (tSC) is gradually increased from 3 μs in steps until DUT fails. The increment step is set to 0.5 μs for 400 V, 0.3 μs for 600 V and 0.1 μs for 800 V, respectively. The short-circuit current waveforms for the five devices tested under a high bus voltage of 800 V are illustrated in Figure 16. The peak current varies among different WJFET designs. For Device A1–A3 with narrow WJFET designs, the peak current is higher than the other two designs, resulting in a shorter SCWT. Additionally, in Device A2, an interlayer crack is observed after the SC test under 800 V in Figure 17a,b.

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    Figure 16. The SC current waveforms of five types of devices with different JFET widths at Vds = 800 V.

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    Figure 17. (a) The hot spot is observed under OBIRCH (Optical Beam Induced Resistance Change) of Device A2 at drain voltage of 800 V. (b) The cross-section at hot spot is prepared by FIB (Focus Ion Beam) of Device A2 at drain voltage of 800 V.

    The SCWT tested under different bus voltages is summarized in Figure 18a. The energy can be calculated using short-circuit current waveforms and device voltage waveforms. The calculated results are plotted in Figure 18b. Devices with different JFET widths have almost the same SCWT under drain voltages of 600 and 800 V. The WJFET has a significant effect on the SCWT when the drain voltage is 400 V. For higher bus voltage conditions, the difference in SCWT among the five designs is significantly reduced.

    In addition, at higher bus voltages, the maximum short-circuit energy that device can safely dissipate is reduced to 33%, as shown in Figure 18b. This is because the short-circuit current multiplied by a high bus voltage generates a significant amount of heat on a very short time scale (<1 μs), causing the device junction temperature to rise rapidly. Thus, the SCWT and total energy are decreased.

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    Figure 18. (a) The SCWT of five types of devices with different JFET widths. (b) The SC energy of five types of devices with different JFET widths.

    4. Discussion

    The on-resistance and short-circuit withstanding time are crucial parameters for SiC MOSFETs, representing their conduction performance and reliability, respectively. It has been reported that the structure designs (JFET region width in this work) can influence both the on-resistance and short-circuit withstanding time. Furthermore, there exists a trade-off relationship between the on-resistance and SCWT, which will be discussed in this section. Figure 19 summarizes the on-resistance and SCWT parameters for each device (Device A1–A5 with different WJFET designs).

    The SCWT test results for the three bus voltage conditions (400, 600 and 800 V) are also illustrated in the figure. For each bus voltage, increasing the WJFET from 2 to 3 μm results in a decrease in device on-resistance from 1.68 to a minimum of 1.48 Ω (a reduction of 11.9%). However, a further increase in WJFET will raise the on-resistance, which is unacceptable. On the other hand, observing the SCWT parameters for the 400 V bus voltage condition (red lines in Figure 19), we can observe a slight drop from Device A1 to A3 (11.7%), followed by a significant drop from A3 to A5 (35.2%). The impact of WJFET designs on SCWT is negligible for higher bus voltages.

    The bus voltage is usually determined by the power electronic system and circuit designs in practical applications. The saturation current primarily indicates the short-circuit current. The short-circuit current and saturation current are positively correlated. In SiC MOSFETs, the saturation current is influenced by two factors: the JFET region’s pinch-off voltage and the MOSFET channel’s saturation voltage. Short-circuit simulations are used to evaluate the potential under the gate oxide. With a wider JFET width, the potential at the JFET side increases, leading to an increase in channel saturation current due to the Drain-Induced Barrier Lowering effect.

    Additionally, a lower pinch-off voltage results in a smaller saturation current in the JFET region. When the JFET region becomes sufficiently narrow, the saturation current of the JFET region becomes the primary factor. For 1200 V–rated SiC MOSFETs, the bus voltage can be selected between 400~800 V or even out of this range. In conclusion, the optimal design of WJFET is 3 μm for the 1200 V SiC MOSFETs studied in this work, without considering an enhanced doping concentration for the JFET region.

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    Figure 19. The relationship between on-resistance and SC withstanding time (SCWT) of different devices with varied JFET width.

    Under high bus voltage conditions, devices with various JFET widths exhibit similar short-circuit behavior. As the JFET region becomes depleted during the short-circuit test, the resistances in the JFET region become relatively small compared to the channel resistance. Therefore, the JFET width has less impact on the result. Furthermore, it can be concluded that the variation in JFET width is not highly sensitive to the short-circuit withstand capability under high bus voltage, but it exhibits a greater impact under low bus voltage conditions. Moreover, Device A3 demonstrates the best performance within the voltage range of 400 to 800 V.

    The relationship between the short-circuit test results at temperatures of 25 and 100 °C and the on-resistance under a 400 V bus voltage is shown in Figure 20 and will be discussed in the following paragraphs. In Section 3.2, the failure reason for DUTs under a high-temperature SC test is clarified. Failure mode is summarized in Figure 21. The failure of a wide WJFET device is due to gate oxide burnout tested in SC under room temperature. As the temperature increases, the failure mode changes to the ILD crack.

    When the temperature is above 100 °C, the device failure mode becomes the same. When evaluating the performance of devices operated at high temperatures, the static resistance gradually increases with temperature, while the short-circuit duration time at high temperatures varies. The devices with wider WJFET inhibit the injection of hot electrons at an elevated temperature, thereby reducing the formation of defects caused by hot carriers.

    Therefore, there is an improvement in SCWT. When the width of the JFET is less than 3.0 μm (A3), due to the increase in the junction temperature in the high-temperature test, the temperature in the interlayer dielectric reaches the critical value faster, resulting in a reduction in the short-circuit withstand time. If the temperature rises to 150 °C, the SCWT for WJFET devices may all decrease due to the failure mode being changed to the ILD crack mode.

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    Figure 20. The relationship between on-resistance and SC withstanding time (SCWT) of devices with varied JFET width at 25 and 100 °C.

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    Figure 21. Summary of the failure mode of devices with different WJFET.

    Judging from the trade-off relationship between the on-resistance and short-circuit current at room temperature and high temperature, devices with WJFET larger than 3.0 μm are more suitable for operating at high temperatures. These devices exhibit a gradual increase in resistance at high temperatures, resulting in an improved short-circuit performance to a certain extent.

    5. Conclusions

    In this paper, 1200 V SiC MOSFETs with various WJFET are fabricated, followed by a comprehensive comparison and study of the short-circuit robustness of these devices. Devices with narrow and wide WJFET exhibit distinct failure mechanisms. The ILD crack is observed in the device with narrow WJFET, while the breakdown of gate oxide is found in the device with wider WJFET after device failure. The relationship between on-resistance and SCWT of devices A1–A5 with different JFET widths is summarized.

    Device A3 demonstrates the best performance in terms of SCWT and on-resistance characteristics, making it an improved design. Furthermore, devices with narrowed JFET widths have limitations in improving SCWT (<20 μs) under a bus voltage of 400 V. The relationship between the short-circuit test results at temperatures of 25 and 100 °C and on-resistance under a bus voltage of 400 V is also investigated. Devices with WJFET larger than 3.0 μm exhibit improved SCWT under high temperatures and are better suited for high temperature operation. As the temperature rises, their resistance shows a slow increment, contributing to an enhanced short-circuit performance to a certain degree.

    Authors

    Hongyi Xu, Baozhu Wang, Na Ren, Hu Long, Kai Huang and Kuang Sheng

    Original – MDPI

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