-
STMicroelectronics has been named a Global Top Employer for 2026 by Top Employers Institute, marking the company’s second consecutive year receiving the certification.
This year, STMicroelectronics is one of only 17 organizations worldwide to earn Global Top Employer status. The recognition covers ST entities in 41 countries and reflects performance across Top Employers Institute’s HR Best Practices Survey, which assesses six domains: People Strategy, Work Environment, Talent Acquisition, Learning, Diversity, Equity & Inclusion, and Wellbeing, followed by rigorous validation and audit at both corporate and country levels.
“Top Employer is an annual certification, and its global renewal for the second consecutive year underscores ST’s commitment to best-in-class people practices. In a period marked by significant external challenges, the improved scores recognized by this certification highlight the strength of our HR strategy and our determination to offer an attractive and engaging work environment worldwide,” said Rajita D’Souza, President, Human Resources and Corporate Social Responsibility, STMicroelectronics.
“Achieving Global Top Employer status in 2026 is an extraordinary accomplishment that reflects excellence in individual countries and, crucially, sustained people practices across regions and worldwide,” said Adrian Seligman, CEO, Top Employers Institute. “STMicroelectronics has demonstrated a rare ability to align its people strategy globally while ensuring meaningful, locally relevant experiences for employees in every certified market—this achievement places STMicroelectronics among a select group of employers setting the benchmark for people strategy internationally.”
The global certification is the highest level of recognition offered by Top Employers Institute. Certified organizations gain access to globally benchmarked insights, data-driven recommendations, expert validation, and proven best practices that strengthen people strategy. Benefits include enhanced employer branding, clearer strategic focus, improved decision making, and stronger ability to demonstrate impact to leaders, boards, and talent markets, as well as opportunities to connect with a global community of certified Top Employers.
Original – STMicroelectronics
-
GlobalFoundries (GF) announced the appointment of Ganesh Moorthy, former president and CEO of Microchip Technology Inc., to its board of directors.
Moorthy brings more than four decades of semiconductor experience, including transformative leadership at Microchip Technology, where he served as CEO, president and board member until his retirement in November 2024. He previously held senior roles including COO and executive vice president, and earlier spent 19 years at Intel in engineering and executive positions across manufacturing, product innovation and customer-focused execution.
“Ganesh’s deep understanding of semiconductor technology, manufacturing at scale and corporate growth will be a tremendous asset to GF as we continue to execute our strategy and expand our leadership in essential semiconductor technologies,” said Dr. Thomas Caulfield, Executive Chairman of GlobalFoundries. “His leadership experience will help us accelerate innovation and strengthen GF’s role as a trusted partner delivering essential technologies that bring intelligence into the real world.”
“GlobalFoundries is uniquely positioned to bring intelligence to everyday devices through differentiated, power-efficient semiconductors manufactured at scale,” said Ganesh Moorthy. “I’m excited to work with Tom, Tim and the Board to advance GF’s strategy, deepen customer partnerships and accelerate delivery of the technologies customers need to turn innovation into real-world impact.”
Moorthy currently serves as Chair of the Board of Ralliant and sits on the boards of Celanese, SiTime and Ayar Labs. He previously served for more than a decade on the board of Rogers. His appointment supports GF’s long-term growth strategy and commitment to a resilient manufacturing footprint delivering power-efficient, differentiated technologies to customers worldwide.
Original – GlobalFoundries
-
Mitsubishi Electric Corporation, Institute of Science Tokyo, University of Tsukuba and Quemix Corporation announced a world-first explanation of how hydrogen creates free electrons in silicon through its interaction with specific crystal defects—an advance that can cut power losses in insulated gate bipolar transistors (IGBTs) and open pathways for future ultra-wide bandgap devices.
Using first-principles calculations alongside electrical, optical and ESR measurements, the team showed that when hydrogen binds near the I4 defect (an interstitial silicon pair), it shifts the defect’s electronic states to favor electron release; the electron associated with hydrogen moves to the defect, which then emits a free electron.
Mitsubishi Electric also reported technical demonstrations on 1,200 V-class devices showing total power-loss reductions of 10% in IGBTs and 20% in diodes versus its 7th-generation products—performance gains linked to the newly clarified hydrogen mechanism and complementary substrate thinning.
Beyond silicon, initial calculations suggest the approach could help control electron levels in ultra-wide bandgap materials such as diamond and AlN, which are notoriously difficult to dope, potentially benefiting power semiconductors, RF devices and quantum sensors.
The collaborators aim to extend this mechanism to next-generation materials to further improve device efficiency and support decarbonization goals.
Original – Mitsubishi Electric
-
Mitsubishi Electric Corporation will begin shipping samples on January 21 of four new trench silicon carbide MOSFET bare dies for power electronics equipment, including electric-vehicle traction inverters, onboard chargers, and power supplies for renewable energy such as solar. The new bare dies are designed to help embed advanced SiC devices directly into systems to lower power consumption while maintaining performance.
The devices will be showcased at the 40th Nepcon Japan R&D and Manufacturing show in Tokyo from January 21–23, with additional exhibitions planned in North America, Europe, China, India and other regions.
Growing decarbonization efforts are expanding the market for high-efficiency power electronics. Demand is rising for power semiconductors that enable EV traction inverters and renewable-energy systems to cut losses while preserving performance and quality.
Since 2010, Mitsubishi Electric has shipped SiC power modules that reduce energy use in air conditioners, industrial equipment and railway inverters. To meet the shift toward advanced bare-die integration, the company is introducing four new trench SiC-MOSFET bare dies that leverage a proprietary trench structure to cut power loss by approximately 50% versus planar SiC-MOSFETs. Proprietary manufacturing, including Mitsubishi Electric’s gate oxide film process, suppresses variation in power loss and on-resistance, supporting stable, long-term quality.
Original – Mitsubishi Electric
-
Novel Crystal Technology, Inc., working under NEDO’s “Key and Advanced Technology R&D through Cross Community Collaboration Program” for β-Ga2O3 wafers, power devices and modules, announced a new crystal growth method that eliminates precious-metal crucibles. The Drop-fed Growth (DG) process supplies raw-material melt as droplets, sharply reducing the use of iridium compared with the conventional Edge-defined Film-fed Growth (EFG) method and enabling β-Ga2O3 substrate manufacturing costs to fall to approximately one-tenth of current levels.
The company has demonstrated 95-mm-diameter β-Ga2O3 crystals grown without iridium crucibles. Using induction heating to raise the temperature inside the chamber, the crystal surface (seed crystal) is heated and locally melted by radiation through a shaped aperture that stabilizes the temperature profile and supports scale-up to larger diameters. Continuous droplet feeding of the melt onto the crystal surface, combined with downward pulling, enables steady growth without a precious-metal container.
Key benefits of the DG method include:
- Dramatic reduction in iridium usage by eliminating precious-metal crucibles
- Easier scale-up to large diameters via controlled surface heating and melting
- Continuous feed enabling production of long crystal boules
A 95-mm cylindrical crystal with a 50-mm grown section has been produced; n-type doping was introduced, as indicated by the crystal’s dark-blue coloration. Patent protection for the DG method is in place or underway in multiple jurisdictions, including Japan (Patent No. 7633637; application 2025-061932), the United States (US 11,725,299 B2; US 12,163,246 B2), Europe (EP 3 945 147 A1), and China (CN 114000188 A).
Looking ahead, Novel Crystal Technology plans to increase crystal diameter and quality using DG, targeting shipments of 150-mm (6-inch) β-Ga2O3 substrates in 2029 and 200-mm (8-inch) substrates in 2035. The company expects the method’s cost and scalability advantages to accelerate adoption of β-Ga2O3 for low-loss power devices across medium-voltage applications such as home appliances and EVs, and high-voltage systems including rail and grid infrastructure.
Original – Novel Crystal Technology
-
Efficient Power Conversion (EPC) announced that the EPC2366, a 40 V enhancement-mode GaN (eGaN®) power transistor, has received the EPDT 2025 Product of the Year Award in the Power Transistor category. The recognition highlights EPC’s leadership in GaN technology for high-efficiency, high-power-density systems spanning data centers, robotics and AI infrastructure.
The EPC2366 targets fast-switching, low-loss applications and is positioned as a superior alternative to legacy MOSFETs in 12 VOUT synchronous rectifiers. It features an ultra-low RDS(on) of 0.8 mΩ and a gate-charge-based figure of merit (RDS(on) × QG) < 12 mΩ·nC, enabling simultaneous reductions in conduction and switching losses for high-frequency power conversion.
The device supports 40 V drain-to-source operation (48 V transient), continuous drain current up to 88 A at VGS = 5 V, and ~360 A pulsed. As an enhancement-mode GaN device, it offers easy gate drive while delivering GaN advantages such as zero reverse-recovery charge and very low output capacitance, which reduce deadtime losses and boost half-bridge and synchronous rectifier efficiency.
Thermal performance is optimized via a compact 3.3 × 2.6 mm PQFN with backside thermal pad. Typical thermal metrics include RθJC ≈ 0.6 °C/W and RθJB ≈ 1.8 °C/W; junction-to-ambient ranges from ~54 °C/W on a JEDEC board to ~26 °C/W on EPC’s recommended evaluation layout. With proper PCB copper spreading and layout, the device supports reliable operation up to a 150 °C maximum junction temperature.
To accelerate design-in, EPC offers the EPC90167 half-bridge evaluation board featuring two EPC2366 devices in a low-parasitic layout. The platform supports 7.5–12 V gate drive, standard PWM logic levels, and single- or dual-input PWM modes (with managed deadtime), providing a practical reference for DC-DC converters, motor drives and other high-current, high-speed stages. Clearly marked test points and recommended bring-up procedures help engineers evaluate switching behavior, thermals and system performance quickly.
“The EPC2366 showcases our ongoing commitment to help engineers design smaller, faster, and more efficient systems that meet the power demands of tomorrow,” said Alex Lidow, CEO and co-founder of EPC. EPDT Editor Mike Green added, “The differentiation achieved with this device, in terms of FoM and power density, will be of clear value to next-generation power system design.”
Optimized for secondary-side synchronous rectification in 48 V–12 V LLC converters, the EPC2366’s leading FoM enables higher switching frequencies and improved efficiency, making it a strong fit for high-density power supplies in AI data centers and other performance-driven applications.
Original – Efficient Power Conversion
-
Wolfspeed, Inc. announced successful production of a single-crystal 300 mm (12-inch) silicon carbide wafer. Backed by one of the industry’s largest silicon carbide IP portfolios—more than 2,300 issued and pending patents worldwide—the company is pioneering the transition to 300 mm and setting a path toward future volume commercialization.
The advance represents a meaningful step for next-generation computing platforms, immersive AR/VR systems, and high-efficiency power devices. By extending silicon carbide to 300 mm, Wolfspeed is opening new performance thresholds and manufacturing scalability for demanding semiconductor applications.
“Producing a 300 mm single crystal silicon carbide wafer is a significant technology achievement and the result of years of focused innovation in crystal growth, boule and wafer processing,” said Elif Balkas, Chief Technology Officer at Wolfspeed. “It positions Wolfspeed to support the industry’s most transformative technologies, especially critical elements of the AI ecosystem, immersive augmented and virtual reality systems, and other advanced power device applications.”
Wolfspeed’s 300 mm platform is designed to unify high-volume silicon carbide manufacturing for power electronics with advanced capabilities in high-purity semi-insulating substrates used in optical and RF systems. This convergence enables a new class of wafer-scale integration across optical, photonic, thermal, and power domains.
As AI workloads drive data centers toward their power limits, the 300 mm silicon carbide platform will help integrate high-voltage power delivery, advanced thermal solutions, and active interconnects at wafer scale—pushing system performance beyond conventional transistor scaling. In AR/VR, silicon carbide’s material properties—including mechanical strength, thermal conductivity, and optical refractive control—support compact, lightweight architectures that pair high-brightness displays with effective thermal management.
Beyond AI and AR/VR, moving silicon carbide to 300 mm enhances the ability to scale production of advanced power devices for applications such as high-voltage grid transmission and next-generation industrial systems, improving economics and long-term supply assurance.
“This 300 mm breakthrough is more than a technical milestone—it unlocks new opportunities for silicon carbide as a strategic material,” said Poshun Chiu, Principal Analyst, Compound Semiconductor, Yole Group. “It clearly demonstrates that silicon carbide is advancing to the next level of manufacturing maturity required for the coming decade of electrification, digitalization, and AI, and provides the market with a credible roadmap toward higher-volume production, improved economics and long-term supply assurance.”
Original – Wolfspeed
-
Soitec announced that its Board of Directors has appointed Laurent Rémont as Chief Executive Officer, effective April 1, 2026.
Rémont, 54, currently serves as Senior Vice President at Infineon Technologies, where he led the Radio Frequency and Sensors business. He previously was Chief Technology Officer at Kontron AG and spent more than fifteen years at STMicroelectronics in general management and R&D roles. His international background spans markets central to Soitec’s strategy—including mobile communications, automotive and artificial intelligence—and brings extensive experience managing complex technological and industrial operations.
The Board underscored its intent to build on the Group’s recent progress, enhancing the value of Soitec’s diversified product and technology portfolio—particularly around AI—and seizing opportunities across the semiconductor market. “We are convinced that Laurent Rémont has all the right attributes to lead Soitec into the next stage of its development,” said Frédéric Lissalde, Chairman of Soitec’s Board of Directors. “His knowledge of the semiconductor industry and value chains, upstream and downstream, is a great match for the profile the Board was seeking to oversee implementation of the Group’s strategic priorities. We were particularly impressed by his innovative mindset, his strategic vision and his proven ability to design and deploy transformative roadmaps. I would like to thank Pierre Barnabé for his ongoing commitment during a particularly demanding period for Soitec.”
“I am proud to join Soitec and grateful for the trust placed in me,” said Laurent Rémont. “Our industry is undergoing rapid change, driven by innovation and the emergence of new technologies that are profoundly transforming how we use technology. Soitec plays a key role at the heart of these transformations, and I look forward to working alongside the management team and all employees to build the next phase of the Group’s development.”
Rémont will join Soitec on March 16, 2026, as a special advisor to CEO Pierre Barnabé before succeeding him at the beginning of the following month. Pierre Barnabé, who announced his resignation on October 1, 2025, will step down on March 31, 2026.
The appointment follows a rigorous selection process led by the Board of Directors and recommended by the Board’s Compensation, Nominations and Board Governance Committee. Rémont’s appointment as a director remains subject to shareholder approval at Soitec’s Annual General Meeting in July 2026; subject to that approval, his three-year term as director will commence on that date.
Original – Soitec
-
Aehr Test Systems reported results for its fiscal second quarter ended November 28, 2025, and reinstated guidance for the second half of fiscal 2026.
Fiscal second quarter highlights:
- Net revenue: $9.9 million (vs. $13.5 million in Q2 FY2025)
- GAAP net loss: $(3.2) million, or $(0.11) per diluted share (vs. $(1.0) million, or $(0.03) per diluted share)
- Non-GAAP net loss: $(1.3) million, or $(0.04) per diluted share (vs. non-GAAP net income of $0.7 million, or $0.02 per diluted share)
- Bookings: $6.2 million
- Backlog: $11.8 million as of November 28, 2025; effective backlog $18.3 million including post-quarter bookings
- Total cash, cash equivalents and restricted cash: $31.0 million (vs. $24.7 million at August 29, 2025)
Fiscal first six months:
- Net revenue: $20.9 million (vs. $26.6 million in the first half of FY2025)
- GAAP net loss: $(5.3) million, or $(0.18) per diluted share (vs. $(0.4) million, or $(0.01) per diluted share)
- Non-GAAP net loss: $(1.0) million, or $(0.04) per diluted share (vs. non-GAAP net income of $2.8 million, or $0.10 per diluted share)
- Cash used in operating activities: $1.5 million
CEO Gayn Erickson noted softer-than-anticipated Q2 revenue but highlighted progress across wafer-level burn-in (WLBI) and packaged-part burn-in (PPBI). Based on recent customer forecasts, the company expects second-half bookings between $60 million and $80 million, positioning Aehr for a strong fiscal 2027 beginning May 30, 2026.Operational updates:
- WLBI momentum: Production installations expanded across multiple end markets. A lead AI processor customer requested additional capacity this fiscal year and plans to add systems and transition to Aehr’s fully integrated automatic WaferPak™ aligner for 300 mm wafers.
- New WLBI hardware: Initial high-power fine-pitch WaferPak for AI processors entered testing under a benchmark program with a top-tier AI supplier using FOX-XP™ systems. Two additional AI companies requested WLBI benchmark evaluations.
- Services partnership: Aehr announced a strategic partnership with ISE Labs to deliver advanced wafer-level test and burn-in services for next-generation HPC and AI applications.
- PPBI traction: Growing packaged-part qualification and production burn-in for AI is driving orders for the Sonoma™ ultra-high-power PPBI platform. Fiscal Q3-to-date orders exceed $5.5 million, including initial orders for the next-generation fully automated Sonoma platform from a premier Silicon Valley lab.
- Pipeline and forecasts: New Sonoma wins for HTOL qualification are expected to drive additional capacity at test houses, with at least one customer planning production later this calendar year. The lead PPBI production customer for AI processors forecasts substantial growth in 2026 and beyond, with requested shipments beginning in Q1 fiscal 2027.
- Memory and photonics: WLBI benchmark with a global flash leader demonstrated FOX-XP as a competitive alternative to traditional packaged-part test; proposals extended to High Bandwidth Flash (HBF). In silicon photonics, a lead customer has firmed up a production ramp early in next fiscal year; another large customer finalized a forecast for data center devices with a roadmap to optical I/O.
For the second half of fiscal 2026 (November 29, 2025–May 29, 2026), Aehr expects revenue of $25 million to $30 million and non-GAAP net loss per diluted share between $(0.09) and $(0.05). The company reiterated that diversification beyond silicon carbide for EVs—into AI processors, GaN power, data storage, silicon photonics and flash memory—expands its addressable market and supports long-term growth and profitability.Original – Aehr Test Systems
-
Cambridge GaN Devices appointed Fabio Necco as Chief Executive Officer. The move is intended to accelerate CGD’s expansion into priority markets.
Necco succeeds CGD Co-founder Giorgia Longobardi, who transitions to Chief Marketing Officer while remaining a Director on CGD’s Board and serving on the Advisory Board of the International Semiconductor Industry Group (I.S.I.G.). “I am delighted to welcome Fabio to CGD and hand over the day-to-day leadership of the company while I channel my energy into my passion for bringing advanced, sustainable and energy-efficient power electronics solutions to market,” said Longobardi. “Fabio is the right person with the right skill set to take CGD into its next growth phase.”
Necco joins CGD from onsemi, where he served as vice president and division general manager. He brings more than 25 years of experience across power electronics, applications engineering, vehicle electrification and data centers—areas central to CGD’s strategy. “CGD is at an exciting juncture,” said Necco. “I’m impressed with the company’s progress and am eager to lead the team into the next stages of product development while substantially increasing our presence in key markets.”
CGD develops GaN devices that enable designers to build sustainable, high-efficiency power systems. Its ICeGaN® technology uses a monolithic, single-chip architecture that integrates all necessary components on one die, improving efficiency and performance while simplifying design. The portfolio emphasizes compact, engineer-led devices suited to market-specific requirements such as traction/auxiliary inverters for electric vehicles and industrial power conversion. A focus on bare die, ease of use, robust gate design and parallel operation supports a broad range of power applications.
Original – Cambridge GaN Devices
