MOSFET Tag Archive

  • Infineon Technologies will Power FOXESS Energy Storage Systems and String Inverters

    Infineon Technologies will Power FOXESS Energy Storage Systems and String Inverters

    3 Min Read

    Infineon Technologies AG supplies its power semiconductor devices to FOXESS, a fast-growing leader in the green energy industry and a manufacturer of inverters and energy storage systems. The two sides aim at promoting the development of green energy.

    Infineon will provide FOXESS with its CoolSiC™ MOSFETs 1200 V, which will be used with EiceDRIVER™ gate drivers for industrial energy storage applications. At the same time, FOXESS’ string PV inverters will use Infineon’s IGBT7 H7 1200 V power semiconductor devices.

    The global market for photovoltaic energy storage systems (PV-ES) has grown at a high speed in the last years. As competition in the PV-ES market accelerates, improving power density has become key to success, and how to improve efficiency and power density for energy storage applications has attracted much attention. Infineon’s CoolSiC MOSFET 1200 V and IGBT7 H7 1200 V series power semiconductor devices adopt the latest semiconductor technologies and design concepts that are tailored to industrial applications.

    Mr. Yu Daihui, Senior Vice President and Head of Industrial & Infrastructure of Infineon Technologies Greater China said, “As an industry leader in power semiconductors, we are proud to work closely with FOXESS. We will continue to drive decarbonization by enabling higher power density and more reliable systems for PV-ES applications.”

    Mr. Zhu Jingcheng, Chairman of FOXESS, said, “Thanks to the support of Infineon’s advanced components, FOXESS’ products have been significantly improved in terms of reliability and efficiency. This has been an important driving force for FOXESS’ growth. Infineon’s technical support and product quality have not only strengthened our competitiveness, but also expanded our presence in the market. We are confident about the future and look forward to further cooperation with Infineon to jointly promote the development of the industry and create greater value for our customers.”

    With a high power density, Infineon’s CoolSiC MOSFETs 1200 V can reduce losses by 50 percent and provide ~2 percent additional energy without increasing the battery size, which is especially beneficial for high-performance, lightweight, and compact energy storage solutions. FOXESS’ H3PRO 15 kW-30 kW energy storage series uses Infineon’s CoolSiC MOSFETs 1200 V for all models. Thanks to Infineon’s excellent performance, the H3PRO series has achieved an efficiency of up to 98.1 percent and excellent EMC performance; with superior performance and reliability, the H3PRO series has seen rapid sales growth in the global market.

    Infineon’s TRENCHSTOP IGBT7 H7 650 V / 1200 V series has lower losses and helps improve the overall efficiency and power density of inverters. In high-power inverter projects, high-current mold packaged discrete devices with current handling capability above 100 A can reduce the number of IGBTs in parallel and replace the IGBT module solution, further improving system reliability and reducing costs; in addition, the H7 series has become an industry benchmark for its high-quality performance and greater resistance to humidity.

    At present, FOXESS’ main industrial and commercial model, the R Series 75-110 kW, redefines the overall design of the 100 kW model by using IGBT7 H7 series discretes, and the efficiency of the whole machine can reach up to 98.6 percent. Thanks to the low power loss and high power density of the IGBT7 H7 series in discrete packages, technical problems such as current sharing in the paralleling process can be simplified and optimized.

    Every power device needs a driver, and the right driver can make the design a lot easier. Infineon offers more than 500 EiceDRIVER gate drivers with typical output currents of 0.1 A~18 A and comprehensive protection functions including fast short-circuit protection (DESAT), active Miller clamp, shoot-through protection, fault reporting, shutdown, and overcurrent protection, suitable for all power devices including CoolSiC and IGBTs.

    Original – Infineon Technologies

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  • MCC Semi Introduced New 40 V N-channel MOSFETs

    MCC Semi Introduced New 40 V N-channel MOSFETs

    1 Min Read

    MCC Semi introduced new high-performance 40V N-channel MOSFETs. These components leverage split-gate trench (SGT) technology and full AEC-Q101 qualification in compact packages.

    Both MCU2D8N04YHQ and MCB2D8N04YHQ also boast low on-resistance of only 2.8mΩ, ensuring efficient power management in a diverse range of automotive systems. 

    These versatile MOSFETs in high-demand DPAK and D2PAK packages ensure a seamless upgrade path with minimal changes for integration within existing designs. Adding to their unquestionable performance in harsh conditions, these components have a high operating junction temperature of up to 175°C. 

    Whether it’s a battery management system or electric water pump, these new MOSFETs are up for delivering the ultimate in reliability for challenging automotive applications.

    Features & Benefits:

    • Fully AEC-Q101 qualified
    • Split-gate trench (SGT) technology
    • Low RDS(on)
    • High power density package
    • High junction temperature up to 175℃
    • Available in compact DPAK and D2PAK packages

    Original – Micro Commercial Components

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  • Toshiba Released Two 150 V N-channel U-MOSX-H Series Power MOSFETs

    Toshiba Released Two 150 V N-channel U-MOSX-H Series Power MOSFETs

    2 Min Read

    Toshiba Electronic Devices & Storage Corporation has launched two 150 V N-channel power MOSFET products that use the new generation process “U-MOSX-H series” and are suitable for switching power supplies for industrial equipment—used for such as data centers and communication base stations—and has expanded the lineup. The new products use the surface mount type SOP Advance(N) package and their drain-source On-resistance (max) is 11.1 mΩ for “TPH1100CQ5” and 14.1 mΩ for “TPH1400CQ5.”

    The new products TPH1100CQ5 and TPH1400CQ5 have improved the reverse recovery characteristics that are critical in synchronous rectification applications. In the case of TPH1400CQ5, the reverse recovery charge is reduced by approximately 73 % and the reverse recovery time is approximately 45 % faster compared with Toshiba’s existing TPH1400CQH.

    Used in synchronous rectification applications, TPH1400CQ5 reduces the power loss of switching power supplies and helps improve efficiency. The new products reduce the drain source spike voltage generated between the drain and source when MOSFET is switched, helping to lower EMI in switching power supplies.

    Toshiba will expand its lineup of products and help to reduce power consumption for equipment.

    Applications

    • Switching power supplies (high efficiency AC-DC converters, high efficiency DC-DC converters, etc.)
    • Motor control equipment (motor drives, etc.)

    Features

    • Low reverse recovery charge:
      TPH1100CQ5 Qrr=32 nC (typ.) (-dIDR/dt=100 A/μs)
      TPH1400CQ5 Qrr=27 nC (typ.) (-dIDR/dt=100 A/μs)
    • Fast reverse recovery time: 
      TPH1100CQ5 trr=38 ns (typ.) (-dIDR/dt=100 A/μs)
      TPH1400CQ5 trr=36 ns (typ.) (-dIDR/dt=100 A/μs)
    • High channel temperature rating: Tch (max)=175 °C

    Original – Toshiba

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  • MCC Semi Expands Automotive MOSFET Portfolio

    MCC Semi Expands Automotive MOSFET Portfolio

    1 Min Read

    MCC Semi expands its automotive MOSFET portfolio with the addition of four side-wettable flank components. Available in N-channel and P-channel options, these products deliver high power density in a compact DFN3333 package.

    Full AEC-Q101 qualification is just one way these MOSFETs ensure quality and reliability. Side-wettable flanks enable more reliable soldering during PCB assembly and allow manufacturers to perform automated optical inspections (AOI) to reduce costs while maintaining quality assurance.

    The P-channel MOSFETs MCGWF20P06YHE3 and MCGWF45P04HE3 leverage trench low-voltage (LV) technology and feature RDS(on) from 13mΩ to 26mΩ. And the N-channel solutions MCGWF60N04YHE3 and MCGWF60N06YHE3 utilize split-gate trench technology with RDS(on) from 3.9mΩ to 6mΩ.

    No matter which side-wettable flank MOSFET you choose, you can take advantage of versatility and performance for a diverse array of automotive electronic systems.

    Features & Benefits:

    • AEC-Q101 qualified
    • P-channel powered by trench low voltage (LV) technology
    • N-channel powered by split-gate trench (SGT) technology
    • Low RDS(on)
    • Side-wettable flanks ensure soldering stability
    • Automated optical inspection capability for cost-effective production
    • Compact yet high power density DFN3333 package

    Original – Micro Commercial Components

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  • Infineon Introduced 80 V MOSFET OptiMOS™ 7

    Infineon Introduced 80 V MOSFET OptiMOS™ 7

    2 Min Read

    Infineon Technologies AG introduced the first product in its new advanced power MOSFET technology OptiMOS™ 7 80 V. The IAUCN08S7N013 features a significantly increased power density and is available in the versatile, robust, and high-current SSO8 5 x 6 mm² SMD package.

    The OptiMOS™ 7 80 V offering is a perfect match for the upcoming 48 V board net applications. It is designed specifically for the high performance, high quality and robustness needed for demanding automotive applications like automotive DC-DC converters in EVs, 48 V motor control, for instance electric power steering (EPS), 48 V battery switches and electric two- and three-wheelers.

    Compared to the previous generation, the R DS(on) of the Infineon IAUCN08S7N013 has been reduced by more than 50 percent, and is now the best R DS(on) in the industry with a maximum of 1.3 mΩ. Users benefit from minimized conduction losses, superior switching performance and the highest power density in a 5 x 6 mm² package.

    In addition, the IAUCN08S7N013 also features low package resistance and inductance, as well as a high avalanche current capability. For automotive applications, it has an extended qualification that goes beyond AEC-Q101.

    The IAUCN08S7N013 is in mass-production and available now. More information is available at www.infineon.com/iaucn08s7n013/.

    Original – Infineon Technologies

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  • Infineon Technologies Announced SSO10T TSC Package with OptiMOS™ MOSFET Technology

    Infineon Technologies Announced SSO10T TSC Package with OptiMOS™ MOSFET Technology

    2 Min Read

    Infineon Technologies AG introduced the SSO10T TSC package with OptiMOS™ MOSFET technology. With its direct top-side cooling concept, the package offers excellent thermal performance. This eliminates heat transfer into or through the PCB of the automotive electronic control unit.

    The package enables a simple and compact double-sided PCB design and minimizes cooling requirements and system costs for future automotive power designs. The SSO10T TSC is therefore well suited for applications such as electric power steering (EPS), EMB, power distribution, brushless DC drives (BLDC), safety switches, reverse battery, and DCDC converters. 

    The SSO10T TSC has a 5 x 7 mm² footprint and is based on the established industry standard SSO8, a 5 x 6 mm² robust housing. However, due to its top-side cooling, the SSO10 TSC offers more than 20 percent and up to 50 percent higher performance than the standard SSO8 – depending on the thermal interface (TIM) material used and the TIM thickness. The SSO10T TSC package is JEDEC listed for open market and provides wide second source compatibility. As a result, the package can be introduced quickly and easily as the future standard for top-side cooling.

    The SSO10T package enables a very compact PCB design and reduces the system footprint. It also lowers the cost of the cooling design by eliminating vias, resulting in lower overall system costs and design effort. At the same time, the housing offers high power density and efficiency, thus supporting the development of future-proof and sustainable vehicles.

    Original – Infineon Technologies

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  • Alpha and Omega Semiconductor Announced XSPairFET™ MOSFET for Buck-Boost Converters

    Alpha and Omega Semiconductor Announced XSPairFET™ MOSFET for Buck-Boost Converters

    2 Min Read

    Alpha and Omega Semiconductor Limited announced its AONZ66412 XSPairFET™ MOSFET designed for Buck-Boost converters in USB PD 3.1 Extended Power Range (EPR) applications. The USB PD 3.1 EPR increases the USB-C maximum power up to 240W. AONZ66412 is defined to support the most commonly addressed power range of up to 140W at 28V, with two 40V N-Channel MOSFETs in a half-bridge configuration in a symmetric XSPairFET™ 5mmx6mm package.

    The AONZ66412 can replace two single DFN5x6 MOSFETs, reducing the PCB area and simplifying the layout of the 4-switch buck-boost architecture while enabling a higher efficiency design. These benefits make the AONZ66412 ideal for buck-boost converters in Type-C USB 3.1 EPR applications, including notebook, USB hub, and power bank designs. The AONZ66412 is an extension to the AOS XSPairFET™ lineup that features the latest bottom source packaging technology and lower parasitic inductance for reduced switch node ringing.

    Engineered with integrated high-side and low-side MOSFETs (3.8mOhms maximum on-resistance for each FET) within a DFN5x6 symmetric XSPairFET™ package, the low-side MOSFET source of the AONZ66412 is connected directly to a large paddle on the lead frame. This allows for improved thermals, as this paddle can be directly connected to the ground plane on the PCB. The improved package parasitics make 1MHz operation achievable, allowing inductor size and height to be reduced. AONZ66412 has been tested to achieve 97% efficiency @1MHz in typical USB PD 3.1 EPR conditions of 28V input, 17.6V output, and 8A load conditions.

    “AOS specifically designed the AONZ66412 to meet EPR Type C PD application demands. AONZ66412 will reduce board space and improve power density to achieve the high-efficiency performance goals designers have set for this widely adopted USB-PD Type C application. AOS continues to be a leading innovator of buck-boost architecture solutions,” said Rack Tsai, Marketing Director of MOSFET product line at AOS.

    Original – Alpha and Omega Semiconductor

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  • A Novel Asymmetric Trench SiC MOSFET with a Poly-Si SiC HJD for Optimizing Reverse Conduction Performance

    A Novel Asymmetric Trench SiC Metal–Oxide–Semiconductor Field-Effect Transistor with a Poly-Si/SiC Heterojunction Diode for Optimizing Reverse Conduction Performance

    16 Min Read

    Abstract

    In this paper, a novel asymmetric trench SiC MOSFET with a Poly-Si/SiC heterojunction diode (HJD-ATMOS) is designed to improve its reverse conduction characteristics and switching performance. This structure features an integrated heterojunction diode, which improves body diode characteristics without affecting device static characteristics.

    The heterojunction diode acts as a freewheeling diode during reverse conduction, reducing the cut-in voltage (Vcut-in) to a lower level than conventional asymmetric trench SiC MOSFET (C-ATMOS), while maintaining a similar breakdown voltage. Meanwhile, the split gate structure reduces gate-to-drain charge (Qgd). Through TCAD simulation, the HJD-ATMOS decreases Vcut-in by 53.04% compared to the C-ATMOS. Both Qgd and switching loss are reduced, with a decrease of 31.91% in Qgd and 40.29% in switching loss.

    1. Introduction

    The wide bandgap semiconductor properties of silicon carbide (SiC) make it a promising candidate for the development of future power switching devices. This is primarily due to SiC possessing properties such as a strong breakdown field, high physical and chemical stability, high thermal conductivity, and high electron saturation velocity.

    SiC devices can operate in harsh environments due to their wide band gap of 3.25 eV and high thermal conductivity of 5 W/(cm·K). The SiC MOSFET is the most significant SiC power switching device due to its lack of trail current. This reduces switching loss and radiator volume, improving system power density.

    SiC MOSFETs commonly make use of parasitic body-PN diodes as freewheeling diodes (FWD) in power inverter and converter systems. However, parasitic body-PN diodes in SiC MOSFETs are not ideal for use as freewheeling diodes. The reasons for this are as follows: Stacking faults (SFs) in SiC devices may cause reliability issues and increase conduction loss.

    Although recent papers concerning the measured degradation of SiC MOSFETs show a high level of current threshold (about 5× the nominal current or more than 1000 A/cm2) for the starting of bipolar degradation, bipolar degradation effects can still occur in SiC MOSFETs under large cyclic pulse current densities. This will limit the application of SiC MOSFET devices in key areas, such as the surge current that flows through a diode during the start-up of a power converter, which can be more than ten times its rated current.

    Furthermore, the body diode’s Vcut-in voltage (~2.7 V) is much higher than that of its silicon counterparts due to SiC’s wide bandgap. To overcome the drawbacks of parasitic body-PN diodes, numerous approaches have been devised to deactivate them. One approach is to integrate SiC MOSFETs with Schottky barrier diodes (SBDs). However, the use of external diodes not only introduces parasitic inductance, limiting switching frequency, but also consumes additional area in the package. And Schottky contacts suffer from a significant increase in reverse leakage current at high temperatures.

    Furthermore, SiC MOSFETs with low-barrier and heterojunction diodes are available. Heterojunction diodes formed between polysilicon and SiC are attractive. Shenoy and Baliga, and Yamagami et al. presented studies on heterojunction diodes using P-Poly-Si and n-6H-SiC, and Poly-Si and 4H-SiC, respectively.

    Both studies demonstrated low-forward-voltage Schottky-like characteristics. Ni et al. proposed a trench SiC MOSFET integrating polysilicon/SiC HJD, exhibiting excellent freewheeling diode (FWD) performance in both the first and third quadrants. The HJD’s unipolar behavior, similar to that of a Schottky diode, effectively suppresses the turn-on of the problematic body diode, mitigating the aging degradation observed in conventional SiC MOSFETs.

    Additionally, HJDs reduce reverse recovery voltage and losses, enhancing long-term operational reliability. Furthermore, HJD integration eliminates the need for a separate SBD, leading to a smaller chip area, simpler packaging, and reduced overall system cost. This also minimizes parasitic inductance arising from additional components.

    A novel asymmetric trench SiC MOSFET with a heterojunction diode at the right of the gate trench is proposed and simulated in this paper. The structure includes a trench gate with split-gate electrodes and a thicker P-Poly-Si layer, resulting in reduced gate charge and improved switching performance. To suppress the depletion layer, an n-type doped current spreading layer (N-CSL) is formed under the entire P-well region.

    To maintain the breakdown voltage (BV) of the device structure while maintaining transfer and output characteristics similar to those of C-ATMOS, the depth of the P-well on the right side is not changed. The N-channel (Nch) is positioned below the P-Poly-Si and in contact with the CSL. The integrated HJD structure of the proposed device eliminates the requirement for an anti-parallel SiC SBD during reverse conduction. The HJD turns on at a low source–drain voltage (Vsd), thus eliminating bipolar degradation by inactivating the body diode. The split gate results in a decrease in gate charge, leading to a reduction in switching losses in the HJD-ATMOS without affecting other characteristics.

    2. Device Structure and Mechanism

    The schematic cross section of HJD-ATMOS and C-ATMOS is shown in Figure 1. Similar to C-ATMOS, the device forms an inversion layer channel in the first quadrant to facilitate electron conduction. The N-CSL layer on the N-drift region reduces the on-resistance. Deep P-wells are used to reduce the electric field stress in the gate oxide at the trench bottom and corner.

    The primary distinction is the body diode structure. The Nch region under the P-Poly-Si provides a low-barrier path for electrons. Meanwhile, the HJD-ATMOS has a split gate and HJD structure on the right of the gate oxide layer. The split gate structure uses only a portion of the trench space for the gate electrode, while the other part is thicker P-Poly-Si that forms a portion of the HJD structure. The HJD-TMOS facilitates low-voltage conduction by allowing electrons to cross the lower heterojunction barrier in the third quadrant. The structure of Nch and N-channel doping concentration (Nnch) will be further discussed based on this optimization in this paper. Device specifications are presented in Table 1.

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    Figure 1. Schematic cross section of (a) HJD-ATMOS and (b) C-ATMOS.

    Table 1. Main parameters used in the simulation.

    Table 1. Main parameters used in the simulation.

    Sentaurus TCAD simulations are used to analyze the performances of the HJD-ATMOS and the C-ATMOS, considering doping and temperature-dependent Shockley–Read–Hall and Auger recombination, doping-dependent transport, impact ionization, band narrowing, high-field velocity saturation, and mobility degradation, as well as fixed charges at the SiC/SiO2 interface for closer simulation results to experimental data.

    The energy band diagram of the P-Poly-Si/N-SiC heterojunction at thermal equilibrium is shown in Figure 2b. The energy band diagram at thermal equilibrium along the A-A’ cut-line is shown in Figure 2a. The heterojunction has a conduction energy gap of 0.46 eV and a valence barrier energy gap of 1.78 eV. The electron barrier height ΦBN is determined by the Fermi level energy Ef and the conduction band peak energy Ec, which is about 1.39 eV. 

    Figure 2c shows the simulated carrier density at the heterojunction interface under forward bias at the rated voltage. Electrons are injected from N-SiC to P-poly, but there are few holes from P-poly to N-SiC due to the high hole barrier. Therefore, the HJD exhibits unipolar action, similar to the SBD.

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    Figure 2. (a) Schematic cross section of HJD-ATMOS; (b) energy band diagram at thermal equilibrium along the A-A’ cut-line; (c) carrier density of the HJD when forward biased at rated voltage.

    We also constructed a 3D band diagram of the device to better observe the working state of the device. Figure 3a shows the 3-D conduction band energy distribution of the device at Vds = 10 V and Vgs = 15 V. The band energy of Nch is higher than that of N-CSL, which prevents electron current from flowing to P-poly and enables the device to work normally like C-ATMOS. 

    Figure 3b shows the distribution of the devices when Vds = −5 V and Vgs = −5 V. The band energy of Nch is lower than that of N-CSL, resulting in electron current flowing from N-CSL to P-poly and preventing the turn-on of parasitic body-PN diodes.

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    Figure 3. Three-dimensional conduction band energy distribution between P-poly, gate, Nch, N-CSL, and P-well (a) when conduction is forward and (b) when conduction is reverse.

    Figure 4 shows the distribution of the total current density, hole current density, and electron current density of the device. From the total current density distribution, it can be seen that the current does not flow from P-Poly-Si to P-well. But a high current density is also noted at the gate corner of P-Poly-Si, which should be noted in use. From the hole current density distribution, it can be seen that holes do not enter N-drift.

    This is due to the difference in the band gap between SiC and polysilicon. Since the energy barrier height between the SiC and polysilicon junctions in the valence band is very large, in the HJD-ATMOS, electron current can move toward the source while hole current cannot move toward the drain. The device can operate normally at electron current densities of 10 A/cm2 and 500 A/cm2.

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    Figure 4. (a) Total current density distribution, (b) hole current density distribution, and (c) electron current density distribution at low and high current in the reverse conduction.

    Figure 5 shows the I–V curves of HJD-ATMOS and C-ATMOS in forward and reverse conduction at room temperature. The steeper slope of the I–V curve of HJD-ATMOS in the first quadrant indicates that its specific on-resistance (Ron,sp) is lower than that of C-ATMOS. This is because the presence of Nch in HJD-ATMOS results in a smaller depletion region of P-well on N-CSL, leading to a wider current conduction region.

    According to the calculations, at Vgs = 15 V and Ids = 200 A/cm2, the Ron,sp values for HJD-ATMOS and C-ATMOS are 1.35 mΩ∙cm2 and 1.46 mΩ∙cm2, respectively. In the third quadrant, at Ids= −10 A/cm2, HJD-TMOS exhibits a significantly lower Vcut-in of only 1.39 V compared to the PN diode of C-TMOS. As a result, HJD-ATMOS is capable of reducing switching losses.

    The rated operating current of the device in the third quadrant is generally Ids = −200 A/cm2. This means that the proposed HJD-ATMOS has a clear advantage over C-ATMOS in that it can start working at a lower voltage. The hole density distribution diagram in Figure 5 for Ids = −200 A/cm2 shows that the integrated HJD effectively suppresses minority carrier injection, reducing bipolar degradation.

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    Figure 5. First and third quadrant characteristics of HJD-ATMOS and C-ATMOS.

    In Figure 6, the local magnification shows that the HJD-ATMOS is affected by current spikes due to leakage. The figure demonstrates the change in breakdown voltage as a function of h and w when Nnch is, respectively, 2 × 1017 cm−3 and 2.5 × 1017 cm−3. It can be observed that when Nnch is 2.5 × 1017 cm−3, with h at 0.25 μm and w at 0.5 μm, the spike in the current is large, indicating the occurrence of leakage. When Nnch is 2.5 × 1017 cm−3, increasing h to 0.30 μm and w to 0.4 μm also results in leakage.

    However, when Nnch is 2.0 × 1017 cm−3 and h increases to 0.3 μm, the device does not exhibit leakage, demonstrating that variations in Nnch have a significant impact on device performance. As shown in Figure 7, Vcut-in varies significantly with h. The minimum point of Vcut-in is 1.31 V at Nnch = 2 × 1017 cm−3, which is lower compared to its value of 1.71 V at Nnch = 2.5 × 1017 cm−3 and h = 0.2 μm.

    This point represents the critical condition for the device not exhibiting leakage when Nnch = 2.5 × 1017 cm−3. After h is greater than 0.25 μm, the variation in Vcut-in with h tends to be flat, and if the value of h is larger, the protective effect of P-well on the gate oxide will also be weakened, and it will also increase the difficulty of process manufacturing.

    As can be seen from Figure 8, when the device Vds is 0 V, Nnch is 2.5 × 1017 cm−3, and h is 0.25 μm, the HJD-ATMOS has more leakage than the device with Nnch is 2.0 × 1017 cm−3 and h is 0.30 μm. The darker regions in the current density plot for the HJD-ATMOS with Nnch at 2.5 × 1017 cm−3 and h at 0.25 μm are larger than those with Nnch at 2.0 × 1017 cm−3 and h at 0.30 μm, indicating higher leakage currents. This also confirms the hypothesis that the breakdown voltage spike is caused by heterojunction leakage. So the results indicate that Nnch = 2 × 1017 cm−3h = 0.3 μm, and w = 0.5 μm are the optimal values.

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    Figure 6. The breakdown voltage varies with hw, and Nnch, when Nnch is 2.0 × 1017 cm−3 and 2.5 × 1017 cm−3h is 0.20 μm, 0.25 μm and 0.30 μm, and w is 0.1 μm to 0.5 μm, respectively.

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    Figure 7. Vcut-in varies with hw, and Nnch, when Nnch is (a) 2.0 × 1017 cm−3, and (b) 2.5 × 1017 cm−3.

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    Figure 8. Current density distribution when (aNnch is 2.5 × 1017 cm−3h is 0.25 μm, and (bNnch is 2.0 × 1017 cm−3h is 0.30 μm at Vds = 0 V.

    3. Simulation Results and Discussion

    Figure 9 shows the capacitances of HJD-ATMOS and C-ATMOS. Gate voltage was fixed at 0 V, a 1 MHz AC signal was applied, and drain voltage was swept from 0 to 1000 V. HJD-ATMOS has lower gate-to-source capacitance (Cgs) than C-ATMOS due to the smaller contact area with the source caused by the split gate structure. HJD-ATMOS’s gate-to-drain capacitance (Cgd) does not decrease.

    This is because the P-well blocks the right side of the gate of C-ATMOS, performing a similar function as the split gate. Therefore, it can be observed that the Ciss (Cgs + Cgd) of the HJD-ATMOS with split gates is also smaller than that of the C-ATMOS.

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    Figure 9. The device capacitance of HJD-ATMOS and C-ATMOS.

    Gate-to-drain charge (Qgd) is critical for power device switching speed in device applications. Figure 10 shows a test circuit to simulate HJD-ATMOS and C-ATMOS gate charges during turn-on. The miller plateau height of HJD-ATMOS is less than that of C-ATMOS, indicating that the threshold voltage of HJD-ATMOS is smaller than that of C-ATMOS.

    Because the gate charge is proportional to the gate capacitance, the HJD-ATMOS has a lower gate charge (Qg) and Qgd compared with the C-ATMOS. The Miller platform in HJD-ATMOS is shorter because of the reduced gate area. The Qgd values for HJD-ATMOS and C-ATMOS are 32 nC/cm2 and 47 nC/cm2, respectively. Qgd of HJD-ATMOS decreased by 31.91% compared to C-ATMOS. Reduced Qgd leads to a smaller high-frequency figure of merit in HJD-ATMOS.

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    Figure 10. The gate charge characteristics of HJD-ATMOS and C-ATMOS.

    Figure 11 shows the electric field distribution at the breakdown of HJD-ATMOS and C-ATMOS. The electric field at the gate oxide of HJD-ATMOS is smaller than that of C-ATMOS. This is because the presence of the Nch introduces a portion of the electric field into this region, which alleviates the electric field that the gate oxide withstands.

    Although increasing the electric field at the heterojunction raises leakage current risk, it is a trade-off for improved reverse conduction performance. Figure 12 shows the blocking characteristics of the HJD-ATMOS and the C-ATMOS at room temperature and high temperature. At room temperature, the data are represented by solid lines, whereas at elevated temperatures, they are depicted by dashed lines. HJD-ATMOS and C-ATMOS have similar breakdown voltages at room temperature. But the leakage current of the HJD-ATMOS increases at high temperature due to the increased thermal energy of the charge carriers.

    The generation of leakage currents, as demonstrated and discussed in Figure 6 and Figure 8, arises due to leakage occurring at the heterojunction, where higher Nnch and greater values of thickness h both contribute to this effect. By improving the semiconductor material growth process, reducing defects and traps, and enhancing the material quality and interface integrity, it is possible to mitigate non-ideal scattering and trap effects experienced by charge carriers at the heterojunction interface, thus suppressing the leakage current.

    While the HJD-ATMOS structure does indeed experience leakage under temperature influence, this leakage is within acceptable limits, with the level of leakage current being 1 × 10−5 μA/cm2.

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    Figure 11. Electric field distribution for the HJD-ATMOS and the C-ATMOS at BV.

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    Figure 12. Blocking characteristics of the HJD-ATMOS and the C-ATMOS.

    Figure 13 shows a double pulse test circuit for investigating switching characteristics. This is a common circuit configuration employed in device testing. Stray inductance is 10 nH, and load inductance is 80 μH. The gate voltage source (Vg) is turned on from −5 V to 15 V at t = 16 µs and turned off from 15 V to 0 V at t = 11 µs. 

    Figure 14 shows the switching waveforms of devices. The switching speed of the HJD-ATMOS is faster than that of the C-ATMOS with an external SBD diode, which results in a smaller switching loss. Figure 15 compares the switching losses between the two devices. In HJD-ATMOS, the turn-on loss (Eon) is 0.26 mJ/cm2, and the turn-off loss (Eoff) is 0.41 mJ/cm2, which demonstrate a reduction of 62.32% and 4.65%, respectively, compared to C-ATMOS.

    The total switch loss of HJD-ATMOS is reduced by 40.29% compared to C-ATMOS. This is due to the smaller Qgd compared with the C-ATMOS. Reduced switching losses in power electronic devices are instrumental in improving operational longevity and reliability. As losses during switching are directly proportional to heat generation, a significant decrease in these losses curtails thermal build-up, mitigating the risk of device overheating and extending its operational life.

    This reduction also sustains lower junction temperatures, crucial for preventing material degradation in high-power-density applications where maintaining low operating temperatures is vital for ensuring long-term stability and reliability. Furthermore, minimizing switching losses allows power converters and similar equipment to function efficiently at elevated frequencies without sacrificing efficiency, empowering designers to develop compact, lightweight systems while consistently meeting reliability standards.

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    Figure 13. A circuit for simulating switching with a double pulsed test.

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    Figure 14. The switching characteristics of HJD-ATMOS and C-ATMOS, including the (a) turn-on process and (b) turn-off process.

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    Figure 15. Switching loss comparison of IJ-ATMOS and C-ATMOS.

    The majority of the process steps for HJD-ATMOS, including epitaxial growth, N+ source and P-well implantation, trench etching, P-base implantation, isolation oxidation, gate oxidation, polysilicon gate deposition, and metallization, are fully compatible with the manufacturing processes of C-ATMOS.

    The N-channel region is formed by ion implantation at the bottom of the trench after trench etching. The split gate is formed by etching after trench oxidation, resulting in a thin layer of oxide between the gate and the P-Poly-Si. The gate-P-Poly-Si trench isolation layer is formed by thermal oxidation, and the trench oxide layer is fully etched and filled with P-Poly-Si.

    Table 2 compares the HJD-ATMOS and the C-ATMOS in terms of their main characteristics. Dynamic FOM indicates the value of Ron,sp × Qgd. The HJD-ATMOS performs better due to the integrated HJD structure.

    Table 2. Device characteristics comparison.

    Table 2. Device characteristics comparison.

    4. Conclusions

    This paper proposes a novel asymmetric trench SiC MOSFET with a heterojunction diode. The performance of HJD-ATMOS and C-ATMOS is compared in detail. It can be observed that HJD-ATMOS demonstrates superior third-quadrant performance with a lower Vcut-in because of the integrated HJD. Compared with C-ATMOS, the Qgd of HJD-ATMOS has decreased by 31.91%. This is because the split gate design further reduces the total gate charge, which reduces the switching loss of the HJD-ATMOS device without affecting other key characteristics.

    As a result, HJD-ATMOS eliminates bipolar degradation and reduces the turn-on loss from 0.69 mJ/cm2 in C-ATMOS to 0.26 mJ/cm2. With its advantageous features, HJD-ATMOS is a strong contender for power electronic applications.

    Authors

    Yiren Yu, Zijun Cheng, Yi Hu, Ruiyi Lv, Shengdong Hu.

    Original – MDPI

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  • MCC Semi Unveiled a New 100V N-channel MOSFET

    MCC Semi Unveiled a New 100V N-channel MOSFET

    1 Min Read

    MCC Semi unveiled the latest innovation tailored specifically for the demanding automotive industry. Powered by 100V, MCU62N10YHE3 is the N-channel MOSFET that packs superior performance and handling into a small DPAK package.

    Precision and efficiency come standard in this power MOSFET solution that features split-gate trench technology and RDS(on) of only 11mΩ. Made to withstand harsh automotive environments, this AEC-Q101 qualified component can handle 62A current capability and operating junction temps up to 175⁰C.

    The ultra-compact package and ideal handling make this new MOSFET an effective solution for more than just the automotive sector. Engineers can rely on its powerful capabilities for consumer, industrial, and renewable energy applications.

    Features & Benefits:

    • AEC-Q101 qualification drives confidence
    • Split-gate trench (SGT) technology enhances performance
    • RDS(on) of only 11mΩ boosts efficiency
    • 62A current capability ensures performance
    • Compact DPAK package saves space and money
    • Junction temperature up to 175℃ for reliability in harsh conditions

    Original – Micro Commercial Components

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  • MCC Semi Delivers New Automotive Grade MOSFETs

    MCC Semi Delivers New Automotive Grade MOSFETs

    1 Min Read

    Micro Commercial Components introduced the latest auto-grade N-channel power MOSFETs with up to 2.5mΩ on-resistance: MCACL220N06YHE3, MCACL2D5N06YL, MCACL280N04YHE3, and MCACL330N04YHE3.

    Optimized for high current output, these powerful components boast RDS(on) as low as 0.8mΩ in a sleek, engineer-friendly DFN5060 package. You can enhance power management and ramp up efficiency with minimal losses and the confidence that come along with AEC-Q101 qualification and the MCC name. 

    With high power density, MCC’s new 40V and 60V MOSFETs are designed to handle harsh conditions and operating junction temps up to 175℃ with ease, making them ideal for diverse automotive and industrial applications — from battery management systems and electric power steering to lighting controls, water pumps, and solar power systems.  

    Features & Benefits:

    • AEC-Q101 qualified for reliability
    • Advanced split-gate trench (SGT) technology
    • Excellent thermal performance & efficiency
    • Low RDS(on) minimizes power losses
    • High power density packagey
    • High junction temperature up to 175℃
    • Compact DFN5060 package saves space and material costs

    Original – Micro Commercial Components

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