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Synopsys, Inc. and GlobalFoundries announced a new collaboration to launch an educational ‘chip design to tapeout’ program for universities worldwide. Aligned with both GFLabs’ and Synopsys Academic & Research Alliances’ (SARA) missions to advance semiconductor innovation through R&D and academic collaboration, this pilot initiative gives researchers, professors and students hands-on access to real-world chip design and manufacturing. By dramatically lowering the cost barrier to custom silicon, the program enables academic institutions to turn their design concepts into working silicon, expanding opportunities for education, research and workforce development.
Forty universities worldwide are participating in the sponsored open-source 180MCU pilot launching this fall. Synopsys will provide comprehensive support including professional-grade electronic design automation (EDA) tools, training and design collateral leveraging the Synopsys Cloud design platform. Once designs are finalized, GF will manufacture the chips through its GlobalShuttle Multi-Project Wafer Program, which aggregates designs from multiple institutions onto a single wafer for fabrication.
“Partnering with GlobalFoundries to bring a full ‘chip design to tapeout’ course to universities is a game changer,” said Dr. Patrick Haspel, executive director of SARA at Synopsys. “This collaboration will empower students with practical, hands-on experience using advanced tools and technologies – skills that are critical to drive innovation in the semiconductor industry. Together, we’re not just teaching design – we’re building the next generation of engineers who will shape the future of silicon.”
As Synopsys and GF seek to evolve this workforce development initiative further, the next phase of the tapeout is focused on bringing these technologies directly into classrooms and embedding hands-on design and testing into academic course curriculum. With the goal of having students collaborate in a design class, Synopsys will provide training to professors on how to lead this course. Following a shuttle run, the second course will dive into classroom testing with chips returned for the next semester.
“This program reflects our deep commitment to advancing semiconductor innovation and cultivating the next generation of talent,” said Bika Carter, director of external R&D at GF. “By giving students and researchers the opportunity to bring their designs from concept to silicon, we’re enriching chip design education and helping shape the future of our industry. We’re proud to partner with Synopsys to empower the talented minds driving tomorrow’s breakthroughs.”
This design enablement collaboration is supported by Synopsys’ SARA program, which provides software, cloud environments, training and curriculum to equip students with latest technology and learning materials. The new Synopsys-GF collaboration exemplifies the SARA program’s commitment to partner on semiconductor workforce development initiatives and nurture talent pipelines worldwide. Along with providing participating universities with essential tools and cloud environment access, the SARA program will also offer comprehensive course content and training.
The tapeout education pilot is just one aspect of GF’s University Partnership Program, which serves to close the prototyping gap in academia and expand access to new technologies to support technological innovation in the semiconductor industry. In its work with more than 80 universities, 110 professors and 600 students, the program selects projects aligned with GF’s R&D roadmap priorities to support research breakthroughs in areas including radio frequency, radar, quantum computing, silicon photonics, sensors and more.
The combination of Synopsys and GlobalFoundries brings together industry-leading EDA design tools and advanced manufacturing, empowering academic institutions to offer students an integrated, real-world journey through the semiconductor process.
Original – GlobalFoundries
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Micro Commercial Components (MCC) has announced the release of its latest 650V ultra-fast rectifiers, available in 40A (MUR4065B-BP) and 60A (MUR6065BL-BP) TO-247AD packages. Engineered for high-speed switching applications, these devices deliver exceptional efficiency and reliability, even under demanding operating conditions.
With an ultra-fast reverse recovery time of just 50 ns, the new rectifiers minimize energy loss and enhance overall system efficiency. Their robust surge-forward-current capability and soft recovery characteristics ensure low-EMI performance, making them ideal for applications that demand stable, high-performance rectification and fast response.
Built on a planar structure die, the devices guarantee consistent long-term operation in challenging thermal and electrical environments. They support high-frequency operation for more compact and efficient system designs and feature a maximum junction temperature rating of 175°C for reliable performance in elevated heat conditions.
Key Features & Benefits
- 650V repetitive peak reverse voltage
- Ultra-fast reverse recovery time (≤50 ns)
- High surge forward current handling
- Planar structure die for long-term reliability
- Soft recovery to reduce EMI and oscillations
- High operating junction temperature up to 175°C
- Available in TO-247AD package
These new MCC rectifiers are designed to support a wide range of power conversion and protection applications, including renewable energy systems, industrial power supplies, and other high-speed switching designs where efficiency and thermal stability are critical.
Original – Micro Commercial Components
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iDEAL Semiconductor has announced the first of its 200 V family of SuperQ™-based MOSFETs has entered mass production, with four additional 200 V devices now sampling.
SuperQ is the first major advance in silicon MOSFET technology in more than 25 years, breaking through long-standing limits in switching and conduction. It delivers a step-change in performance and efficiency while preserving the core advantages of silicon: ruggedness, high-volume manufacturability, and proven reliability at 175 °C.
The first 200 V device to reach mass production, the iS20M028S1P, is a 25 mΩ MOSFET in a TO-220 package. iDEAL’s lowest-resistance 200 V devices, now sampling in TOLL and D²PAK-7L, achieve a maximum RDS(on) of just 5.5 mΩ. This sets a new performance benchmark, delivering resistance that is 1.2x lower than the current market leader and 1.7x lower than the next-best competitor.
“By expanding SuperQ into 200 V, iDEAL is proving that silicon innovation is far from over,” said Mark Granahan, CEO and Founder of iDEAL Semiconductor. “These results show that we can deliver the lowest resistance and superior switching behavior while maintaining the manufacturability, reliability, and cost advantages of silicon. It’s a major milestone for our company and for customers looking to push efficiency forward.”
Target applications for the 200 V SuperQ family include motor drives, LED lighting, battery protection, AI servers, isolated DC/DC power modules, USB-PD adapters, and solar. With devices now in production and industry-leading samples available, iDEAL is accelerating engagement with customers across high-growth power markets.
Original – iDEAL Semiconductor
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ROHM and Schaeffler have started mass production of a new high-voltage inverter brick equipped with ROHM’s SiC (silicon carbide) MOSFET bare chips as part of their strategic partnership. The inverter brick is intended for a major Chinese car manufacturer.
The Schaeffler inverter subassembly is the essential power device building block (brick) to control the electric drive via logic signals. This is where the high-frequency current pulses are produced that set the vehicle’s electric motor in motion. The performance characteristics of the inverter brick now being produced are impressive: Schaeffler increased the output of the brick by increasing the maximum possible battery voltage to much more than the usual 800 V – and with RMS currents of up to 650 A, which turn the sub-module into a compact power pack.
“Through our strategic approach of incorporating scalability and modularity into our e-mobility solutions – from individual components to a highly integrated electric axle – we developed the readily integrated inverter brick. Based on our generic platform development, it took us just one year to bring this optimal product for the popular X-in-1 architectures to volume production readiness,” says Thomas Stierle, CEO of the E-Mobility Division at Schaeffler.
As a core component of an inverter, a brick has to meet strict requirements. The characteristics of the sub-module are indicative of the factors behind the current sales success and start of volume production: ROHM’s silicon carbide (SiC) power semiconductors enable the frame-mounted sub-module with high power density to be compact, efficient, and readily integrated into various inverters through its modular and scalable design. The sub-module incorporates the power module for pulse width modulation (PWM) of the current pulses, the DC link capacitor, a DC link and a cooler. Moreover, the brick has a DC boost function, thanks to which a vehicle with 800 V architecture can also be charged at a 400 V charging station at a charging speed of 800 V.
“We are glad about the launch of volume production for Schaeffler’s inverter brick with our 4th generation SiC MOSFET,” says Dr. Kazuhide Ino, Member of the Board and Managing Executive Officer at ROHM. “With our SiC technology we are making a substantial contribution to increasing the efficiency and performance of electric cars. Working with Schaeffler as our partner, we are thus fostering innovation and sustainability in the automotive industry,” Dr. Ino adds.
The strategic partnership of Schaeffler (originally initiated under Vitesco Technologies) with ROHM has existed since 2020 and serves to secure capacity for energy-efficient SiC power semiconductors.
Original – ROHM
