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JEDEC Solid State Technology Association announced the publication of JEP198: Guideline for Reverse Bias Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices. Developed by JEDEC’s JC-70.1 Gallium Nitride Subcommittee, JEP198 is available for free download from the JEDEC website.
JEP198 presents guidelines for evaluating the Time Dependent Breakdown (TDB) reliability of GaN power transistors. It is applicable to planar enhancement-mode, depletion-mode, GaN integrated power solutions, and cascode GaN power transistors.
This publication covers suggested stress conditions and related test parameters for evaluating the TDB reliability of GaN power transistors using the off-state bias. The stress conditions and test parameters for both High Temperature Reverse Bias Stress and Application Specific Stress-Testing are designed to evaluate the reliability of GaN transistors over their useful lifetime under accelerated stress conditions.
“We are becoming more dependent on power electronics in all facets of our daily lives. As such, the technologies behind those systems are advancing and so too must the device-specific qualification processes. The new GaN-focused Guideline for Reverse Bias Reliability Evaluation is a critical step toward achieving that goal,” said Ron Barr, VP of Quality and Reliability, Transphorm and Co-Chair of the Task Group 701_1.
“This was a collaborative effort conducted by both GaN semiconductor and end product manufacturers. I’m proud of the work the task group delivered. It is an important framework to ensure cross-industry uniformity that will, in the end, provide power system manufacturers the necessary confidence when designing with GaN devices.”
“With the rise of renewable energy and electrification of our lives, the efficiency of power semiconductors is becoming more critical. This is where GaN power semiconductors have proven to be a valuable technology. The Guideline for Reverse Bias Reliability Evaluation is another step in improving confidence in GaN Technology and the products that are on and being brought to market,” said Dr. Kurt Smith, VP of Reliability and Qualification at VisIC Technologies and Chair of JC-70.1.
“This document was developed through collaboration of the multi-corporation team of industry experts to represent the best practices for evaluating GaN devices. It was a long multi-year process to reach consensus and the team is to be commended for the quality document and all of the hard work that went into it.”
Original – JEDEC
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MIT and Applied Materials, Inc. announced an agreement today that, together with a grant to MIT from the Northeast Microelectronics Coalition (NEMC) Hub, commits more than $40 million of estimated private and public investment to add advanced nano-fabrication equipment and capabilities to MIT.nano, the Institute’s center for nanoscale science and engineering.
The collaboration will create a unique open-access site in the United States that supports research and development at industry-compatible scale using the same equipment found in high-volume production fabs to accelerate advances in silicon and compound semiconductors, power electronics, optical computing, analog devices and other critical technologies.
The equipment and related funding and in-kind support provided by Applied Materials will significantly enhance MIT.nano’s existing capabilities to fabricate up to 200mm (8-inch) wafers, a size essential to industry prototyping and production of semiconductors used in a broad range of markets including consumer electronics, automotive, industrial automation, clean energy and more. Positioned to fill the gap between academic experimentation and commercialization, the equipment will help establish a bridge connecting early-stage innovation to industry pathways to the marketplace.
“A brilliant new concept for a chip won’t have impact in the world unless companies can make millions of copies of it. MIT.nano’s collaboration with Applied Materials will create a critical open-access capacity to help innovations travel from lab bench to industry foundries for manufacturing,” said Maria Zuber, MIT’s Vice President for Research and E. A. Griswold Professor of Geophysics. “I am grateful to Applied Materials for its investment in this vision. The impact of the new toolset will ripple across MIT and throughout Massachusetts, the region, and the nation.”
Applied Materials is the world’s largest supplier of equipment for manufacturing semiconductors, displays and other advanced electronics. The company will provide at MIT.nano several state-of-the-art process tools capable of supporting 150 and 200mm wafers and will enhance and upgrade an existing tool owned by MIT. In addition to assisting MIT.nano in the day-to-day operation and maintenance of the equipment, Applied engineers will develop new process capabilities which will benefit researchers and students from MIT and beyond.
“Chips are becoming increasingly complex, and there is tremendous need for continued advancements in 200mm devices, particularly compound semiconductors like silicon carbide and gallium nitride,” said Aninda Moitra, Corporate Vice President and General Manager of Applied Materials’ ICAPS Business. “Applied is excited to team with MIT.nano to create a unique, open-access site in the U.S. where the chip ecosystem can collaborate to accelerate innovation. Our engagement with MIT expands Applied’s university innovation network and furthers our efforts to reduce the time and cost of commercializing new technologies while strengthening the pipeline of future semiconductor industry talent.”
The Northeast Microelectronics Coalition (NEMC) Hub, managed by the Massachusetts Technology Collaborative (MassTech), will allocate $7.7 million to enable the installation of the tools. The NEMC is the regional “hub” that connects and amplifies the capabilities of diverse organizations from across New England plus New Jersey and New York. The U.S. Department of Defense (DoD) selected the NEMC Hub as one of eight Microelectronics Commons Hubs and awarded funding from the CHIPS and Science Act to accelerate the transition of critical microelectronics technologies from lab-to-fab, spur new jobs, expand workforce training opportunities and invest in the region’s advanced manufacturing and technology sectors.
The Microelectronics Commons program is managed at the federal level by the Office of the Under Secretary of Defense for Research and Engineering (OUSD(R&E)) and the Naval Surface Warfare Center, Crane Division, and facilitated through the National Security Technology Accelerator (NSTXL), which organizes the execution of the eight regional hubs located across the country. The announcement of the public sector support for the project was made at an event attended by leaders from the DoD and NSTXL during a site visit to meet with NEMC Hub members.
“The installation and operation of these tools at MIT.nano will have a direct impact on the members of the NEMC Hub, the Massachusetts and Northeast regional economy, and national security. This is what the CHIPS and Science Act is all about,” said Ben Linville-Engler, Deputy Director at the MassTech Collaborative and the interim director of the NEMC Hub. “This is an essential investment by the NEMC Hub to meet the mission of the Microelectronics Commons.”
MIT.nano is a 200,000 square-foot facility located in the heart of the MIT campus with pristine, class-100 cleanrooms capable of accepting these advanced tools. Its open-access model means that MIT.nano’s toolsets and laboratories are available not only to the campus but also to early-stage R&D by researchers from other academic institutions, non-profit organizations, government and companies ranging from Fortune 500 multinationals to local startups. Vladimir Bulović, faculty director of MIT.nano, said he expects the new equipment to come online in early 2025.
“With vital funding for installation from NEMC and after a thorough and productive planning process with Applied Materials, MIT.nano is ready to install this toolset and integrate it into our expansive capabilities that serve over 1,100 researchers from academia, startups, and established companies,” said Bulović, who is also the Fariborz Maseeh Professor of Emerging Technologies in MIT’s Department of Electrical Engineering and Computer Science (EECS). “We’re eager to add these powerful new capabilities and excited for the new ideas, collaborations, and innovations that will follow.”
As part of its arrangement with MIT.nano, Applied Materials will join the MIT.nano Consortium, an industry program comprising 12 companies from different industries around the world. With the contributions of the company’s technical staff, Applied Materials will also have the opportunity to engage with MIT’s intellectual centers, including continued membership with the Microsystems Technology Laboratories (MTL).
Original – Applied Materials
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Power Integrations announced the release of the InnoSwitch™5-Pro family of high-efficiency, programmable flyback switcher ICs. The single-chip switcher achieves over 95 percent efficiency with a novel secondary-side control scheme which achieves zero-voltage switching (ZVS) without a dedicated and costly additional high voltage switch.
The new IC, which features a 750 V or a 900 V PowiGaN™ primary switch, primary-side controller, FluxLink™ isolated feedback and secondary controller with an I2C interface, optimizes the design and manufacture of compact, highly efficient single- or multi-port USB PD adapters. Applications are notebooks, high-end cellphones and other portable consumer products, including designs that require the new USB PD EPR (Extended Power Range) protocol.
Adnaan Lokhandwala, senior product marketing manager at Power Integrations said: “The combination of ZVS and GaN is power supply magic. Switching losses vanish, and we can leverage the low conduction losses of GaN to implement super dense adapter layouts with far fewer components than asymmetric half-bridge (AHB) circuits or active clamp alternatives. For example, we have demonstrated 140 W / 28 V USB PD adapters in 4.2 cubic inches using only 106 components. The flyback topology used by InnoSwitch5-Pro ICs is much easier to implement than AHB and can also operate from universal mains with or without a PFC stage.”
InnoSwitch5-Pro flyback switcher ICs feature lossless input line voltage sensing on the secondary side for adaptive DCM/CCM and ZVS control to maximize efficiency and simplify design across line and load. The ICs also feature a post-production tolerance offset to facilitate accurate output constant-current (CC) control of better than two percent to support the UFCS protocol.
Excellent efficiency – better than 95 percent – allows designers to eliminate heat sinks, spreaders and potting materials for thermal management, further reducing size, weight, component cost and manufacturing complexity. Key markets for the InnoSwitch5-Pro family of flyback switcher ICs include high-density USB PD 3.1 Extended Power Range (EPR), UFCS and multi-protocol adapters, notebook adapters and after-market single- and multi-port chargers and adapters.
Original – Power Integrations
