Power Circuits for Clean Switching and Low Losses

This tutorial focuses on managing and minimizing parasitic inductance in modern power electronic systems—a key challenge as power density, switching speed, and efficiency demands continue to rise. Unipolar devices, especially wide bandgap semiconductors, require exceptionally low parasitic inductance for clean and reliable switching. This event will explore the root causes and effects of parasitic elements, particularly their impact on overvoltage, current waveforms, device paralleling, gate drive performance, and system-level losses.

Attendees will receive foundational knowledge of switching behavior in inductive circuits and dive into practical aspects like conductor geometry, layout techniques, and real-world case studies. The program includes focused sessions on system optimization for low inductance and reduced losses, all presented in English.

Technical Chair:
Dr. Reinhold Bayerer, Physics of Power Electronics

Main Topics Covered:

• Basics of switching inductive loads and waveform interpretation

• Influence of parasitic inductance on IGBTs, MOSFETs, and diodes

• Current sharing in paralleled devices

• Gate circuit inductance and short-circuit implications

• Geometry-driven design for low parasitic inductance

• Oscillations in snubber/DC-link systems

• Case studies on asymmetric paralleling

• Measurement techniques and practical PCB examples

• Parasitic capacitance and EMI considerations

Why Attend:

• Understand how parasitic inductance and resistance impact switching behavior and system losses

• Learn how to design for clean switching in high-speed, high-density power systems

• Explore real-world examples of device paralleling, gate drive issues, and EMI mitigation

• Get practical insight into layout, conductor geometry, and measurement challenges

• Enhance your design strategies for Si and WBG-based systems

• Suitable for design engineers, system architects, and application engineers in power electronics

Draft Schedule Highlights:

• Day 1: Parasitics fundamentals, layout geometry, impact on switching and losses, paralleling effects

• Day 2: Gate inductance, DC-bus oscillations, measurement strategies, EMI and capacitance topics

• Interactive sessions on participant-specific interests