Toshiba Electronic Devices & Storage Corporation has developed a new trench-gate silicon carbide (SiC) MOSFET technology that simultaneously reduces on-resistance and improves short-circuit robustness, addressing one of the key trade-offs in high-performance SiC power devices.
The innovation centers on optimizing the bottom p-well structure beneath the trench gate and refining the design of the junction field-effect transistor (JFET) region, including its width and doping concentration. By narrowing the JFET width and increasing doping levels, Toshiba demonstrated suppression of short-circuit current and reduced short-circuit energy generation inside the device.
The company confirmed that this approach lowers internal temperature rise during fault events while maintaining gate oxide reliability, a critical requirement for long-term SiC device durability. Prototype devices achieved approximately 25% lower on-resistance compared with conventional trench-gate SiC MOSFETs while preserving short-circuit robustness.
This development is particularly important because trench-gate SiC MOSFETs are widely favored for their low conduction losses and high current density, but balancing efficiency with short-circuit survivability has remained a major design challenge. Toshiba’s findings establish a new design methodology focused on minimizing short-circuit energy as a path toward improved reliability and efficiency.
The technology targets demanding high-efficiency power conversion applications including electric vehicles, renewable energy systems, industrial power supplies, and AI data center infrastructure, where both efficiency and fault tolerance are critical.
Commercialization is already underway, with test samples of the 1200 V trench-gate SiC MOSFET “TW007D120E” shipping earlier this month. Toshiba will present additional technical details at ISPSD 2026 in Las Vegas.
Original – Toshiba