Navitas Semiconductor announced the launch of its 5th-generation GeneSiC technology platform, built around a new high-voltage silicon carbide Trench-Assisted Planar (TAP) MOSFET architecture. The company said the platform will underpin an industry-leading 1200 V MOSFET family and complements its 4th-generation GeneSiC ultra-high-voltage portfolio at 2300 V and 3300 V, targeting applications such as AI data centers, grid and energy infrastructure, and industrial electrification.
According to Navitas, the 5th-generation platform uses its most compact TAP architecture to combine planar-gate ruggedness with improved performance enabled by a trench structure in the source region. The design focus is to raise efficiency while supporting long-term reliability in high-voltage power conversion.
Navitas said the new 1200 V technology delivers a 35% improvement in the RDS,ON × QGD figure of merit versus the prior-generation 1200 V platform, reducing switching losses and enabling cooler operation and higher switching frequencies. High-speed switching performance is further supported by an approximately 25% improvement in the QGD/QGS ratio. Combined with a stable high threshold voltage specification (VGS,TH ≥ 3 V), the company positions the platform as more immune to parasitic turn-on in high-noise environments.
The 5th-generation technology also targets dynamic performance through an optimized RDS(ON) × EOSS characteristic and adds “Soft Body-Diode” technology intended to improve commutation behavior and reduce electromagnetic interference (EMI) in fast-switching power stages.
For reliability, Navitas said this generation is qualified to an “AEC-Plus” grade for long-term stability in demanding infrastructure applications. The company highlighted extended stress testing for static high-temperature, high-voltage conditions, dynamic reliability tests intended to reflect fast-switching mission profiles, and a focus on threshold voltage stability over prolonged switching stress. Navitas also cited extreme gate oxide reliability, with an extrapolated gate-oxide failure time exceeding 1 million years at operating VGS of 18 V and 175°C, and enhanced cosmic ray robustness aimed at lowering FIT rates for high-uptime environments. Navitas noted that “AEC-Plus” indicates parts exceeding AEC-Q101 and JEDEC standards for reliability testing based on Navitas test results.
“Our customers are redefining the boundaries of power conversion in AI data centers and energy infrastructure, and Navitas is marching along with them in every step of the way,” said Paul Wheeler, VP & GM of Navitas’ SiC Business Unit. “Significant technological improvements in our 5th generation GeneSiC technology underscore Navitas’ commitment to delivering industry-leading performance and reliability in silicon carbide MOSFETs.”
Navitas said a white paper on Trench-Assisted Planar technology is available from the company, and that additional 5th-generation GeneSiC product announcements are expected in the coming months.
Original – Navitas Semiconductor