-
onsemi announced a new family of vertical gallium nitride (vGaN) power semiconductors intended to raise efficiency, power density, and ruggedness across high-demand applications, including AI data centers, electric vehicles, renewable energy, and aerospace and defense. Developed at the company’s Syracuse, New York facility, the GaN-on-GaN technology conducts current vertically through the device to support higher operating voltages and faster switching frequencies.
According to onsemi, the vGaN architecture can reduce conversion losses by nearly 50 percent versus current solutions while enabling smaller and lighter power systems through higher-frequency operation. The company holds more than 130 global patents related to vertical GaN covering process, device architecture, manufacturing, and systems innovations.
Key points
• Technology: GaN-on-GaN structure conducts current vertically, designed for high voltage and high-frequency switching
• Efficiency: Potential to cut power losses by almost 50 percent while improving thermal performance and power density
• Footprint: Devices are described as approximately three times smaller than commercially available lateral GaN alternatives
• Sampling: Initial 700 V and 1,200 V devices are sampling to early access customersTarget applications
• AI data centers: Higher-density 800 V DC-DC stages to improve cost per rack and reduce component count
• Electric vehicles: Smaller, lighter, and more efficient traction inverters
• Charging infrastructure: Faster, more compact, and rugged charging systems
• Renewable energy: Higher-voltage solar and wind inverter stages with lower losses
• Energy storage systems: High-density, bidirectional converters for batteries and microgrids
• Industrial automation: More efficient, cooler motor drives and robotics
• Aerospace, defense, and security: Compact, high-reliability power platformsMost GaN power devices are built on non-GaN substrates such as silicon or sapphire and conduct laterally across the surface. onsemi’s vGaN uses a GaN substrate and a vertical current path, which increases voltage handling, improves thermal stability, and enhances ruggedness under extreme operating conditions. The vertical approach is aimed at enabling higher operating frequencies, shrinking passives such as inductors and capacitors, and reducing overall system size and cooling requirements.
onsemi is currently sampling 700 V and 1,200 V vGaN devices to early access customers. Broader portfolio details and production timelines are expected to follow.
Original – onsemi
-
Taiwan Semiconductor announced a new 1,200 V PLA/PLD diode series aimed at automotive and high-reliability power systems. The devices, rated at 15 A, 30 A, and 60 A, combine a low forward voltage (1.3 Vf max), low reverse leakage (<10 µA at 25 °C), and a high junction temperature rating (Tj max 175 °C) to improve efficiency and thermal headroom in demanding environments.
The portfolio is offered in ThinDPAK, D2PAK-D, and TO-247BD packages, enabling straightforward drop-in replacement in existing layouts. Two models, PLAD15QH and PLDS30QH, are fully AEC-Q qualified for automotive use. All six devices are manufactured to stringent automotive-quality standards.
Target applications span three-phase AC/DC converters, server and computing power systems including AI power shelves, EV charging stations and on-board chargers, Vienna rectifiers, totem-pole and bridgeless PFC topologies, inverters and UPS systems, and general-purpose high-power rectification.
By pairing low conduction loss with controlled leakage and high temperature capability, the PLA/PLD diodes are positioned to boost efficiency, reduce thermal dissipation, and enhance reliability across both new and retrofit power designs.
Original – Taiwan Semiconductor
-
Renesas Electronics reported third-quarter 2025 results showing stable revenue and strong profitability on a non-GAAP basis, alongside IFRS figures that reflect the impact of purchase accounting and other non-recurring items.
Third quarter 2025 (non-GAAP)
• Revenue: 334.2 billion yen
• Gross profit: 192.5 billion yen (gross margin 57.6%)
• Operating profit: 103.2 billion yen (operating margin 30.9%)
• Profit attributable to owners of parent: 88.2 billion yen (margin 26.4%)
• EBITDA: 122.5 billion yen (margin 36.7%)Third quarter 2025 (IFRS)
• Revenue: 335.4 billion yen
• Gross profit: 192.3 billion yen (gross margin 57.3%)
• Operating profit: 72.6 billion yen (operating margin 21.7%)
• Profit attributable to owners of parent: 106.3 billion yen (margin 31.7%)
• EBITDA: 117.4 billion yen (margin 35.0%)Nine months ended September 30, 2025 (non-GAAP)
• Revenue: 967.6 billion yen
• Gross profit: 552.0 billion yen (gross margin 57.1%)
• Operating profit: 278.9 billion yen (operating margin 28.8%)
• Profit attributable to owners of parent: 239.3 billion yen (margin 24.7%)
• EBITDA: 336.3 billion yen (margin 34.8%)Nine months ended September 30, 2025 (IFRS)
• Revenue: 969.7 billion yen
• Gross profit: 546.5 billion yen (gross margin 56.4%)
• Operating profit: 133.9 billion yen (operating margin 13.8%)
• Profit (loss) attributable to owners of parent: negative 69.1 billion yen (margin negative 7.1%)
• EBITDA: 276.7 billion yen (margin 28.5%)The gap between non-GAAP and IFRS results primarily reflects amortization of purchased intangible assets and depreciation of property, plant and equipment, stock-based compensation, and other non-recurring items and adjustments. For the third quarter, these factors reduced IFRS operating profit relative to non-GAAP by 30.6 billion yen; for the nine-month period, the reduction was 145.0 billion yen. On gross profit, reconciliation impacts were modest for the quarter and nine months
Overall, Renesas delivered resilient non-GAAP profitability with gross margins above 57% and operating margins near 31% in the third quarter, while IFRS results capture the accounting effects of one-time and acquisition-related items over the reporting periods.
Original – Renesas Electronics
-
Magnachip Semiconductor announced two 650V Super Junction MOSFET products in a TO-Leadless (TOLL) package engineered for high-power, high-current consumer applications, including premium TVs, gaming monitors, AI laptop adaptors, and fast chargers.
Unlike Magnachip’s existing 80V–200V eXtreme Trench MOSFETs in 3-pin TOLL, the new 650V SJ MOSFETs adopt a 4-pin Kelvin configuration. By separating the gate-source return path, the design reduces parasitic inductance, helping to curb gate ringing, improve switching stability, and raise overall power efficiency—especially at higher dv/dt and di/dt.
Against conventional D2PAK packaging, the 4-pin TOLL format delivers more than a 100% increase in current capability, a 24% reduction in board footprint, and a 48% reduction in height. The result is a compact, thermally efficient package well suited to smaller PCBs and high-power-density products that demand strong heat dissipation.
The new devices are aimed at meeting the dual requirements of space savings and performance in slim form-factor systems. The company plans to broaden its 600V TOLL lineup to support next-generation platforms in AI datacenters and other high-power applications.
Original – Magnachip Semiconductor
-
Infineon Technologies announced EasyPACK™ C, the next generation of its EasyPACK power module family, targeting high-stress industrial applications including fast DC and megawatt EV charging, energy storage systems, and uninterruptible power supplies. The first devices in the new package integrate CoolSiC MOSFETs 1200 V G2 with Infineon’s .XT interconnection technology to deliver higher efficiency, stronger power-cycling performance, and longer service life under fluctuating load profiles.
According to Infineon, designs based on CoolSiC MOSFET G2 in EasyPACK C can achieve more than 30 percent higher power density and up to 20 times longer lifetime compared with prior-generation CoolSiC devices. The second-generation MOSFETs also provide an approximate 25 percent reduction in RDS(on), helping to cut conduction losses and improve thermal headroom at elevated operating currents.
The new housing concept supports higher power density and greater layout flexibility, and it is engineered with a roadmap toward future, higher-voltage classes. The inclusion of .XT interconnection is intended to further extend device lifetime by reducing thermal resistance and improving reliability under rigorous cycling.
EasyPACK C has been engineered for harsh thermal conditions. The modules withstand overload switching up to a junction temperature Tvj(over) of 200°C and support continuous operation up to Tvj(op) of 175°C, aided by a new plastic material and silicone gel system. An updated PressFIT pin design doubles current capacity per pin, lowers PCB-level temperatures, and streamlines assembly. Electrical isolation is rated at 3 kV AC for one minute.
The portfolio launches with multiple topologies, including three-level and H-bridge configurations, and is available with or without integrated thermal interface material to align with different cooling strategies and manufacturing flows.
Initial modules featuring CoolSiC MOSFET G2 in EasyPACK C are available now, with further additions planned to serve a broader range of industrial power architectures.
Original – Infineon Technologies
-
Siltronic AG reported results for the first nine months of 2025 broadly in line with expectations against a challenging market backdrop. Sales for January to September totaled EUR 975.1 million, down 7.3% year on year, reflecting pricing and product-mix effects as well as a weaker US dollar. Third-quarter sales were EUR 300.3 million, an 8.7% sequential decline due mainly to scheduled delivery shifts into the fourth quarter and adverse currency movements.
Management said the company’s strategic initiatives and cost discipline are supporting resilience and underpin the full-year outlook. CEO Dr. Michael Heckmeier noted that Q3 performance was impacted by delivery timing and FX, but nine-month results remained solid and guidance for 2025 is confirmed.
Siltronic’s Q3 sales of EUR 300.3 million were affected by a lower wafer area sold and the depreciation of the US dollar from an average 1.13 per euro in Q2 to 1.17 per euro in Q3. Cost of sales rose 13.0% sequentially to EUR 303.9 million, driven by the start of depreciation and ramp-related costs for the new Singapore fab, and by a favorable spare-parts valuation in Q2 that did not repeat. Gross profit declined to EUR -3.6 million.
The company recorded a positive FX result of EUR 3.2 million in Q3, versus a EUR 3.2 million loss in Q2. EBITDA was EUR 65.7 million, with an EBITDA margin of 21.9% (Q2: 26.3%). EBIT decreased to EUR -31.4 million due to lower EBITDA and higher depreciation. The quarter’s result was EUR -43.9 million, with earnings per share of EUR -1.29.
For the first nine months, sales were EUR 975.1 million versus EUR 1,052.2 million a year earlier, mainly due to price and mix, partly offset by higher wafer volumes. Cost of sales rose 2.5% to EUR 863.7 million, reflecting increased volume and significantly higher depreciation, partly balanced by fixed-cost dilution and savings measures. Gross profit was EUR 111.4 million, with gross margin at 11.4% (prior year: 20.0%).
EBITDA for the period was EUR 230.5 million (prior year: EUR 270.7 million), equating to an EBITDA margin of 23.6% (prior year: 25.7%). Depreciation rose to EUR 223.3 million (prior year: EUR 172.9 million), taking EBIT to EUR 7.2 million (prior year: EUR 97.8 million). The period result was EUR -25.1 million (prior year: EUR 68.8 million), with earnings per share of EUR -0.83 (prior year: EUR 2.19). The FX result improved to EUR 3.2 million from EUR 0.1 million in the comparable period.
Siltronic maintained a solid equity ratio of 42.6% at September 30, 2025 (December 31, 2024: 43.6%). Capital expenditure remained high due to the Singapore fab, but net capex payments decreased to EUR 339.1 million (prior year: EUR 565.1 million). Free cash flow improved to EUR -202.6 million from EUR -324.1 million, and net cash flow to EUR -186.9 million from EUR -317.7 million. Operating cash flow declined by EUR 104.5 million year on year, driven by lower EBITDA and a planned inventory build ahead of Q4 deliveries. Net financial debt was EUR 932.7 million (December 31, 2024: EUR 733.5 million), which the company expects to be the peak level for the year.
Siltronic reaffirmed full-year guidance, incorporating a less favorable FX assumption of 1.17 EUR/USD for H2. Management continues to expect sales to be mid single-digit percent below 2024. The EBITDA margin outlook has been specified to 22–24% (previously 21–25%). Ranges for depreciation and capital expenditure have been narrowed to EUR 340–360 million and EUR 360–380 million, respectively. Expectations for EBIT (significant decline year on year) and net cash flow (considerable improvement, but still negative) remain unchanged.
The company said ongoing execution of strategic initiatives, cost measures, and the ramp of the Singapore fab position Siltronic to serve customer demand reliably as delivery timing normalizes in the fourth quarter.
Original – Siltronic
-
MCC introduced the MCTL1D0N08Y, an 80 V N-channel MOSFET in a compact TOLL-8L package engineered for high-current, fast-switching designs where thermal performance, efficiency, and footprint are critical. With a maximum RDS(on) of 1.0 mΩ at VGS = 10 V and a continuous drain current rating of 320 A, the device is aimed at reducing conduction losses in server-class SMPS, high-current DC-DC converters, industrial motor drives, and energy-storage inverters.
The MOSFET leverages a split-gate trench architecture and a low-parasitic package layout to enable fast, clean transitions that lower switching losses and mitigate EMI. Compared with legacy D2PAK solutions, the TOLL-8L format shortens current paths and improves thermal flow, supporting higher switching frequencies, smaller magnetics and heatsinks, and more compact, reliable assemblies.
Key specifications and design attributes
• Drain-source voltage (VDS): 80 V, providing transient headroom for telecom, data center, and industrial environments
• RDS(on): 1.0 mΩ max at VGS = 10 V for minimized conduction loss and higher efficiency
• Continuous drain current: 320 A for demanding high-current stages
• Package: TOLL-8L with low parasitics for improved switching behavior versus D2PAK
• Thermal performance: RθJA ≈ 40 °C/W; junction temperature Tj(max) = 175 °C for reliable operation at elevated ambient conditions
• Architecture: Split-gate trench design to balance ultra-low on-resistance with high switching speedBy combining very low on-resistance with a high-current, thermally capable package, the MCTL1D0N08Y is positioned to enhance uptime, reduce system losses, and shrink power stages across a wide range of industrial and infrastructure applications.
Original – Micro Commercial Components
-
GlobalFoundries announced plans to invest €1.1 billion to expand manufacturing at its Dresden, Germany site, aiming to lift annual output to more than one million wafers by the end of 2028. The company says the expansion—known internally as project SPRINT—will make Dresden the largest facility of its kind in Europe, strengthening regional supply resilience and supporting fast-growing demand across automotive, IoT, defense, and critical infrastructure.
The program is expected to receive support from the German federal government and the State of Saxony within the framework of the European Chips Act, pending EU approval anticipated later this year. In addition to capacity growth, the site will be upgraded to provide end-to-end European processes and data flows aligned with stringent semiconductor security requirements.
German leaders welcomed the move during a visit to the Dresden campus. Chancellor Friedrich Merz called SPRINT “a commitment to Germany as an industrial and innovation location— and above all to the sovereignty of our country and Europe.” Saxony’s Minister President Michael Kretschmer said the billion-euro expansion underscores “Silicon Saxony’s” status as Europe’s leading microelectronics cluster and enhances European technological independence.
GlobalFoundries notes that recent disruptions—particularly in automotive—have highlighted the vulnerability of global chip supply chains. Scaling Dresden is a core element of the company’s broader strategy to diversify and regionalize manufacturing, with parallel investments underway in Europe, the United States, and other regions. According to CEO Tim Breen, the expansion is designed to provide customers in critical industries with secure supply and differentiated technologies as “physical AI” applications accelerate.
The added capacity will focus on GlobalFoundries’ specialty platforms featuring low-power operation, embedded secure memory, and advanced wireless connectivity. These technologies are central to next-generation vehicles, industrial and IoT systems, and high-reliability infrastructure. The company also expects the site to contribute to ongoing innovation in emerging compute architectures and quantum-related technologies through the next decade.
European partners and customers emphasized the strategic impact. Leaders from Aumovio SE, Bosch, Infineon, NXP, Siemens, and SpiNNcloud pointed to stronger regional resilience, a deeper capabilities ecosystem in Saxony, and faster commercialization cycles for advanced mobility and AI hardware.
The announcement follows GlobalFoundries’ recent participation in the “Made for Germany” initiative, which brings together companies committing long-term industrial investment in the country. Since 2009, the company has invested more than €10 billion in its Dresden operations, making it one of Germany’s largest industrial investments and a foundational asset for Europe’s semiconductor ambitions.
Original – GlobalFoundries
-
From smartphones to autonomous vehicles to AI infrastructure, today’s breakthroughs are built on nanometer-scale structures inside advanced silicon. As devices pack more performance into smaller geometries, minor defects can cascade into costly delays. Addressing that challenge, Thermo Fisher Scientific has introduced the Thermo Scientific Helios MX1 Plasma Focused Ion Beam Scanning Electron Microscope (PFIB-SEM), a system designed to bring high-resolution subsurface analysis directly into the semiconductor fabrication environment.
Helios MX1 enables chipmakers to visualize and interrogate buried logic, memory, and advanced packaging features without leaving the fab. By placing PFIB-SEM capability on the production floor, manufacturers can move from problem identification to insight much faster, reducing the time engineers spend waiting for lab results and accelerating corrective actions.
At the core of the platform is automated 3D reconstruction and metrology. The system mills, images, and measures complex device stacks with minimal operator intervention, generating volumetric datasets that expose defects and variability hidden beneath the wafer surface. This level of automation is intended to increase throughput and consistency while shortening time-to-data—an increasingly important metric as process complexity and analysis demand rise.
Integrating lab-grade instrumentation into production facilities can also improve time-to-yield. By revealing failure mechanisms and structural anomalies early, Helios MX1 supports faster process tuning, tighter control windows, and more reliable ramp schedules across leading-edge nodes and advanced packaging flows.
Thermo Fisher notes that the industry’s need for in-fab analysis has grown sharply, outpacing what traditional workflows can handle. With Helios MX1, fab teams gain a detailed three-dimensional view of subsurface structures where many critical issues originate, helping them make decisions with greater confidence and speed.
Positioned as a fab-ready solution, Helios MX1 is aimed at customers working on applications ranging from medical devices and automated driving to high-performance and AI computing. By enabling rapid, in-situ insight, the system is designed to help manufacturers reduce cycle times, improve device performance, and sustain quality at scale.
For organizations seeking to modernize process control and failure analysis in high-volume manufacturing, Helios MX1 offers a direct path to see more, sooner—without the delays of traditional lab detours.
Original – Thermo Fisher Scientific
-
Infineon Technologies has enhanced its Infineon Power Simulation Platform (IPOSIM) with a SPICE-based model generation tool that elevates system-level accuracy for loss and thermal analysis. The update enables developers to include external circuitry and gate-driver selection directly in their simulations, producing more realistic results for static, dynamic, and thermal performance across a wide range of operating conditions.
By incorporating non-linear semiconductor behavior and real-world parameters such as stray inductance, gate voltage, and dead time, the new capability supports advanced device comparisons early in the design cycle. Engineers can configure the application environment within the workflow, accelerating device selection, shortening time-to-market, and reducing costly hardware iterations. The integrated approach is particularly relevant for applications where switching power and thermal performance are critical, including EV charging, solar inverters, motor drives, energy storage systems, and industrial power supplies.
The SPICE functionality is fully embedded in IPOSIM’s multi-device comparison process. Users can select supported devices, identify compatible gate drivers, and run guided simulations that reflect practical operating scenarios. Models are generated online and are designed to streamline decision-making with system-level fidelity.
IPOSIM with SPICE is available now and free to use with company registration. The initial release supports 1200 V silicon carbide discrete devices in a predefined three-phase, two-level topology, alongside 36 compatible gate drivers. Infineon plans to extend coverage to CoolMOS™, CoolSiC™ modules, OptiMOS™, and GaN devices, with broader gate-driver support to follow.
Original – Infineon Technologies
